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the information in this document is subject to change without notice. data sheet mos integrated circuit m pd17062 document no. ic-3560 (o.d. no. ic-8937) date published january 1995 p printed in japan the m pd17062 is a 4-bit cmos microcontroller for digital tuning systems. the single-chip device incorporates an image display controller enabling a range of different displays, together with a pll frequency synthesizer. the cpu has six main functions: 4-bit parallel addition, logic operation, multiple bit test, carry-flag set/ reset, powerful interrupt, and a timer. the device contains a user-programmable image display controller (idc) for on-screen displays. the different displays can be controlled with simple programs. the device also has a serial interface function, many input/output (i/o) ports controlled by powerful i/o instructions, and 6-bit pulse width modulation (pwm) output for a 4-bit a/d converter and d/a converter. features 4-bit single-chip microcontroller containing pll frequency synthesizer and image display controller ? 4-bit microcontroller for digital tuning system ? internal pll frequency synthesizer: with prescaler m pb595 ?5 v 10% ? low-power cmos ? program memory (rom): 8k bytes (16 bits 3968 steps) ? data memory (ram): 4 bits 336 words ? 6 stack levels ? 35 easy-to-understand instruction sets ? support of decimal operations ? instruction execution time: 2 m s (with an 8-mhz crystal) ? internal d/a converter: 6 bits 4 (pwm output) ? internal a/d converter: 4 bits 6 ? internal horizontal synchronizing signal counter ? internal commercial power frequency counter ? internal power-failure detector and power-on reset circuit ? internal image display controller (idc) (user-pro- grammable) number of characters in display: up to 99 on a single screen display configuration: 14 rows 19 columns number of character types: 120 character format: 10 15 dots (rimming possible) number of colors: 8 character size: four sizes in each of the horizontal and vertical dimensions internal 1h circuit for preventing vertical deflection ? internal 8-bit serial interface (one system with two channels: three-wire or two-wire) ? interrupt input for remote-controller signals (with noise canceler) ? many i/o ports number of i/o ports : 15 number of input ports : 4 number of output ports: 8 1995
2 m pd17062 ordering information part number package m pd17062cu- 48-pin plastic shrink dip (600 mil) m pd17062gc- 64-pin plastic qfp (14 14 mm) remark is the rom code number. function overview item function rom (program memory) capacity 3968 16 bits (masked rom) crom (character rom) capacity 1920 16 bits (included in rom) ram (data memory) capacity 336 4 bits (including the area that can be used for vram) vram (video ram) capacity 224 4 bits (included in ram) instruction execution time 2 m s (when the 8-mhz crystal is used) stack level 6 levels (stack operation possible) number of i/o ports number of input ports: 4 number of output ports: 8 number of i/o ports: 15 idc (image display controller) number of characters in display: up to 99 on a single screen display format: 10 15 dots, 14 rows 19 columns number of character types: 120 (user-programmable) number of colors: 8 character size vertical dimension : 1 to 4 times (can be set for each line) horizontal dimension : 1 to 4 times (can be set for each character) serial interface serial interface 0 (two-wire or i 2 c bus compatible) serial interface 1 (two-wire or three-wire) d/a converter 6 bits 4 (pwm output, withstand voltage of up to 12.5 v) a/d converter 4 bits 6 (successive-approximation converter by software) interrupt external interrupt : 2 channels internal interrupt : 2 channels timer 1 channel (internal clock/zerocross input) pll frequency synthesizer scaling method : pulse swallow method (vco pin: up to 40 mhz), external specialized two-modulus prescaler ( m pb595, for example) reference frequency : 6.25, 12.5, 25 khz charge pump : error-out output phase comparator : capable of unlock detection by a program reset power-on reset reset by the ce pin with power-failure detection function supply voltage 5 v 10% one system 4 channels ? ?
3 m pd17062 pin configuration (top view) 48-pin plastic shrink dip (600 mil) adc 0 to adc 5 : a/d converter input p0d 0 to p0d 3 : port 0d blank : blanking signal output p1a 0 to p1a 3 : port 1a blue : character signal output p1b 0 to p1b 3 : port 1b ce : chip enable p1c 1 to p1c 3 : port 1c eo : error out red : character signal output gnd : ground sck : shift clock input/output green : character signal output scl : shift clock input/output hscnt : horizontal synchronizing signal sda : serial data input/output counter input si : serial data input h sync : horizontal synchronizing signal input so : serial data output int nc : interrupt signal input tmin : timer event input nc : no connection vco : local oscillation input psc : pulse swallow control output v dd : main power supply pwm 0 to pwm 3 : pulse width modulation output v sync : vertical synchronizing signal input p0a 0 to p0a 3 : port 0a x in : clock oscillation p0b 0 to p0b 3 : port 0b x out : clock oscillation p0c 0 to p0c 3 : port 0c 1 3 2 4 6 5 7 9 8 10 12 11 13 15 14 16 18 17 19 21 20 22 24 23 48 46 47 45 43 44 42 40 41 39 37 38 36 34 35 33 31 32 30 28 29 27 25 26 p0c 3 p0c 1 p0c 2 p0c 0 p0d 2 /adc 4 p0d 3 /adc 5 p0d 1 /adc 3 pwm 3 p0d 0 /adc 2 pwm 2 pwm 0 pwm 1 v dd eo vco gnd ce psc x out p1a 3 x in p1a 2 p1a 0 p1a 1 int nc p0a 1 /scl p0a 0 /sda p0a 2 /sck p0b 0 /si p0a 3 /so p0b 1 p0b 3 /hscnt p0b 2 /tmin adc 0 p1c 2 p1c 1 p1c 3 /adc 1 h sync v sync blank green blue red p1b 1 p1b 0 p1b 2 gnd p1b 3 pd17062cu- m
4 m pd17062 64-pin plastic qfp (14 14 mm) 1 3 2 4 6 5 7 9 8 10 12 11 13 15 14 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 46 47 45 43 44 42 40 41 39 37 38 36 34 35 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 pob 2 /tmin adc 0 pob 3 /hscnt p1c 2 nc nc nc p1c 3 /adc 1 nc v sync blank blue nc h sync p1c 1 nc p0d 0 /adc 2 pwm 2 pwm 3 pwm 0 nc nc v dd vco nc eo gnd psc nc nc pwm 1 nc p0d 1 /adc 3 p0d 3 /adc 5 p0d 2 /adc 4 p0c 2 nc p0c 3 nc p0a 0 /sda int nc p0a 1 /sck p0b 0 /si p0b 1 p0a 1 /scl p0a 3 /so p0c 0 p0c 1 ce x in x out nc p1a 0 p1a 1 nc p1b 3 gnd p1b 1 red green p1b 2 p1b 0 p1a 3 p1a 2 pd17062gc- -3be m
5 m pd17062 block diagram vco psc eo h sync v sync red green blue blank p0a 0 /sda p0a 1 /scl p0a 2 /sck p0a 3 /so p0b 0 /si p0b 1 p0b 2 /tmin p0b 3 /hscnt p0d 0 /adc 2 p0d 1 /adc 3 p0d 2 /adc 4 p0d 3 /adc 5 p1c 3 /adc 1 p1c 2 p1c 1 adc 0 pwm 0 pwm 1 pwm 2 pwm 3 p1a 0 p1a 1 p1a 2 p1a 3 p1b 0 p1b 1 p1b 2 p1b 3 p0c 0 p0c 1 p0c 2 p0c 3 int nc x in x out v dd ce gnd cpu peripheral instruction decoder interrupt controller p0c p1b p1a pwm pll idc serial i/o p0a p0b hsync counter timer controller rf ram 336 4 bits (including vram) sysreg alu rom 3968 16 bits (including crom) program counter stack 6 12 bits osc reset p0d p1c a/d
6 m pd17062 contents 1. pins ............................................................................................................................... .............. 11 1.1 pin functions ............................................................................................................................. 11 1.2 equivalent circuits of the pins ........................................................................................ 14 2. program memory (rom) .................................................................................................... 18 2.1 configuration of program memory ............................................................................... 18 2.2 functions of program memory ........................................................................................ 19 2.3 program flow ........................................................................................................................... 19 2.4 branching a program ............................................................................................................ 20 2.6 table reference ........................................................................................................................ 24 2.7 notes on using the branch instruction and subroutine call instruction ............................................................................................. 24 3. program counter (pc) ....................................................................................................... 25 4. stack ............................................................................................................................... ........... 26 4.1 components ............................................................................................................................... .26 4.2 stack pointer (sp) .................................................................................................................... 26 4.3 address stack registers (asrs) ........................................................................................ 27 4.4 interrupt stack registers .................................................................................................. 27 5. data memory (ram) ............................................................................................................. 29 5.1 structure of data memory ................................................................................................ 29 5.2 functions of data memory ................................................................................................. 34 5.3 notes on using data memory ............................................................................................ 38 6. general-purpose register (gr) ...................................................................................... 40 6.1 structure of the general-purpose register ............................................................. 40 6.2 function of the general-purpose register ................................................................ 40 6.3 address generation for general-purpose register and data memory in individual instructions ..................................................................... 42 6.4 notes on using the general-purpose register ......................................................... 46 7. arithmetic logic unit (alu) block ................................................................................ 48 7.1 overview ............................................................................................................................... ....... 48 7.2 configuration and functions of the components of the alu block ............ 49 7.3 alu operations ......................................................................................................................... 49 7.4 notes on using the alu ........................................................................................................ 53 8. system register (sysreg) ................................................................................................. 54 8.1 address register (ar) ............................................................................................................. 55 8.2 window register (wr) ............................................................................................................ 55 8.3 bank register (bank) .............................................................................................................. 56 8.4 memory pointer enable flag (mpe) .................................................................................. 56
7 m pd17062 8.5 index register (ix) and data memory row address pointer (mp) ...................... 57 8.6 general-purpose register pointer (rp) .......................................................................... 66 8.7 program status word (psword) ...................................................................................... 66 9. register file (rf) ................................................................................................................... 67 9.1 idcdmaen (00h, b 1 ) ...................................................................................................................... 75 9.2 sp (01h) ............................................................................................................................... ............ 75 9.3 ce (07h, b 0 ) .............................................................................................................................. ....... 76 9.4 serial interface mode register (08h) .............................................................................. 76 9.5 btm0md (09h) ............................................................................................................................... 77 9.6 intvsyn (0fh, b 2 ) ......................................................................................................................... 77 9.7 intnc (0fh, b 0 ) .............................................................................................................................. 78 9.8 horizontal synchronizing signal counter control (11h, 12h) .......................... 78 9.9 pll reference mode selection register (13h) .............................................................. 79 9.10 setting of intnc pin acceptance pulse width (15h) .................................................. 79 9.11 timer carry (17h) ....................................................................................................................... 80 9.12 serial interface wait control (18h) ................................................................................ 80 9.13 iegnc (1fh) ............................................................................................................................... ..... 80 9.14 a/d convertor control (21h) .............................................................................................. 81 9.15 pll unlock flip-flop judge register (22h) ..................................................................... 81 9.16 port1c i/o setting (27h) .......................................................................................................... 82 9.17 serial i/o0 status register (28h) ....................................................................................... 82 9.18 interrupt permission flag (2fh) ........................................................................................ 83 9.19 crom bank selection (30h) ................................................................................................... 83 9.20 idcen (31h) ............................................................................................................................... ..... 84 9.21 pll unlock flip-flop delay control register (32h) .................................................. 84 9.22 p1bbion (35h) ............................................................................................................................... .85 9.23 p0bbion (36h) ............................................................................................................................... .85 9.24 p0abion (37h) ............................................................................................................................... .86 9.25 setting of interrupt request generation timing in serial interface mode (38h) ................................................................................................. 86 9.26 shift clock frequency setting (39h) ............................................................................... 87 9.27 irqnc (3fh) ............................................................................................................................... ..... 87 10. data buffer (dbf) .................................................................................................................. 88 10.1 data buffer structure ......................................................................................................... 88 10.2 functions of data buffer .................................................................................................... 90 10.3 data buffer and table referencing ................................................................................ 91 10.4 data buffer and peripheral hardware ......................................................................... 93 10.5 data buffer and peripheral registers .......................................................................... 97 10.6 precautions when using data buffers ......................................................................... 104 11. interrupt ............................................................................................................................... .. 106 11.1 interrupt block configuration ........................................................................................ 106 11.2 interrupt function ................................................................................................................. 108 11.3 interrupt acceptance ............................................................................................................ 111 11.4 operations after interrupt acceptance ...................................................................... 116
8 m pd17062 11.5 returning control from interrupt processing routine ..................................... 116 11.6 interrupt processing routine ........................................................................................... 117 11.7 external interrupts (int nc pin, v sync pin) ....................................................................... 121 11.8 internal interrupt (timer, serial interface) .............................................................. 123 11.9 multiple interrupts ................................................................................................................ 124 12. timer ............................................................................................................................... ........... 133 12.1 timer configuration .............................................................................................................. 133 12.2 timer functions ........................................................................................................................ 134 12.3 timer carry flip-flop (timer carry ff) ............................................................................ 136 12.4 cautions in using the timer carry ff ............................................................................. 141 12.5 timer interrupt ......................................................................................................................... 147 12.6 cautions in using the timer interrupt .......................................................................... 151 13. standby ............................................................................................................................... ..... 153 13.1 standby block configuration ........................................................................................... 153 13.2 standby function .................................................................................................................... 154 13.3 device operation mode specified at the ce pin ........................................................... 155 13.4 halt function ............................................................................................................................ 156 13.5 clock stop function ............................................................................................................... 164 13.6 operation of the device at a halt or clock stop .................................................... 167 14. reset ............................................................................................................................... ........... 171 14.1 reset block configuration ................................................................................................. 171 14.2 reset function .......................................................................................................................... 172 14.3 ce reset ............................................................................................................................... .......... 173 14.4 power-on reset ......................................................................................................................... 177 14.5 relationship between ce reset and power-on reset .............................................. 180 14.6 power failure detection ...................................................................................................... 184 15. general-purpose port ....................................................................................................... 189 15.1 configuration and classification of general-purpose port ............................ 189 15.2 functions of general-purpose ports ............................................................................ 191 15.3 general-purpose i/o ports (p0a, p0b, p1b, p1c) ............................................................. 194 15.4 general-purpose input port (p0d) .................................................................................... 198 15.5 general-purpose output ports (p0c, p1a) ..................................................................... 199 16. serial interface .................................................................................................................... 201 16.1 serial interface mode register ........................................................................................ 201 16.2 clock counter ........................................................................................................................... 206 16.3 status register ........................................................................................................................ 207 16.4 wait register ............................................................................................................................. 20 9 16.5 presettable shift register (psr) ....................................................................................... 214 16.6 serial interface interrupt source register (sio0imd) ........................................... 215 16.7 shift clock frequency register (sio0ck) ....................................................................... 216
9 m pd17062 17. d/a converter ....................................................................................................................... 217 17.1 pwm pins ............................................................................................................................... ........ 217 18. pll frequency synthesizer ............................................................................................. 219 18.1 pll frequency synthesizer configuration ................................................................. 219 18.2 overview of each pll frequency synthesizer block .............................................. 220 18.3 programmable divider (pd) and pll mode select register ................................... 221 18.4 reference frequency generator (rfg) .......................................................................... 223 18.5 phase comparator ( f -det), charge pump, and unlock detection block ......... 225 18.6 pll disable mode ....................................................................................................................... 231 18.7 setting data for the pll frequency synthesizer .................................................... 232 19. a/d converter ....................................................................................................................... 233 19.1 principle of operation ........................................................................................................... 233 19.2 d/a converter configuration ........................................................................................... 234 19.3 reference voltage setting register (adcr) ................................................................ 235 19.4 comparison register (adccmp) .......................................................................................... 235 19.5 adc pin select register (adcchn) ...................................................................................... 236 19.6 example of a/d conversion program ............................................................................ 237 20. image display controller ............................................................................................... 240 20.1 specification overview and restrictions .................................................................... 240 20.2 direct memory access ........................................................................................................... 243 20.3 idc enable flag ......................................................................................................................... 245 20.4 vram ............................................................................................................................... ................ 246 20.5 character rom .......................................................................................................................... 255 20.6 blank, r, g, and b pins ............................................................................................................ 263 20.7 specifying the display start position ........................................................................... 264 20.8 sample programs .................................................................................................................... 268 21. horizontal sync signal counter ................................................................................ 274 21.1 horizontal sync signal counter configuration .................................................... 274 21.2 gate control register (hscgt) .......................................................................................... 275 21.3 hsync counter (hsc) ............................................................................................................... 276 21.4 example of using the horizontal sync signal .......................................................... 276 22. instruction sets .................................................................................................................. 277 22.1 outline of instruction sets ............................................................................................... 277 22.2 instructions .............................................................................................................................. 2 78 22.3 list of instruction sets ....................................................................................................... 279 22.4 built-in macro instructions .............................................................................................. 281 23. reserved symbols for assembler ............................................................................... 282 23.1 system register (sysreg) ..................................................................................................... 282 23.2 data buffer (dbf) ...................................................................................................................... 282 23.3 port register ............................................................................................................................. 28 3 23.4 register files ............................................................................................................................. 28 4
10 m pd17062 23.5 peripheral hardware register .......................................................................................... 286 23.6 others ............................................................................................................................... ............ 286 24. electrical characteristics ............................................................................................. 287 25. package drawings ............................................................................................................... 289 26. recommended soldering conditions ....................................................................... 291 appendix development tools ............................................................................................... 292
11 m pd17062 1. pins 1.1 pin functions pin no. dip qfp (gc) symbol description output type at power-on reset p0c 3 | p0c 0 p0d 3 /adc 5 | p0d 0 /adc 2 pwm 3 | pwm 0 v dd v dd1 v dd0 vco eo gnd gnd2 gnd1 gnd0 psc ce x out x in 1 | 4 5 | 8 9 | 12 13 14 15 16 17 18 19 20 58 | 61 62 | 1 2 | 6 9 11 13 15 16 17 18 19 4-bit output port input of port 0d and a/d converter ? p0d 3 to p0d 0 4-bit input port containing a pull-down resis- tor. ? adc 5 to adc 2 input of a 4-bit a/d converter, which is a soft- ware-based successive-approximation type. the reference voltage is v dd . output of a 6-bit d/a converter. the output type is pwm. output is done at a frequency of 15.625 khz. the pin can also be used as a one-bit output port. supplies the power to the device. to enable all functions, 5 v 10% is supplied. to operate only the cpu, 4 v is required. in the clock-stop state, the voltage can be reduced to 3.5 v. when the supply voltage increases from 0 v to 4 v, a power-on reset occurs and the program is started from address 0. apply an identical voltage to all pins. inputs the signal obtained by dividing the local oscillation output by the specialized prescaler. outputs the pll error signal. the signal is input through the external lpf to the local oscillation circuit. grounds the device. connect all pins to ground. outputs the signal to switch the frequency divi- sion ratio of the specialized prescaler. inputs the signal to select the device. to operate the pll and idc, set the input signal high. if the input signal is low, the device can be backed up with a low current drain by executing a stop instruction. when the input signal goes high, the device is reset and the program is started from address 0. used to connect a crystal. an 8-mhz crystal is used. cmos push-pull n-ch open drain cmos tristate cmos push-pull undefined input undefined input hi-z undefined input input
12 m pd17062 pin no. dip qfp (gc) symbol description output type at power-on reset p1a 3 | p1a 0 p1b 3 | p1b 0 red green blue blank h sync v sync p1c 3 /adc 1 p1c 2 p1c 1 adc 0 p0b 3 /hscnt p0b 2 /tmin p0b 1 p0b 0 /si p0a 3 /so p0a 2 /sck p0a 1 /scl p0a 0 /sda 21 | 24 26 | 29 30 31 32 33 34 35 36 | 38 39 40 | 43 44 | 47 20 | 24 27 | 30 31 32 33 34 35 36 38 | 45 46 47 | 50 51 | 54 4-bit output port. this n-ch open-drain output port has an intermediate withstand voltage. 4-bit i/o port. each bit can be set for input or output. outputs the character data corresponding to r, g, and b of the idc display. the output is active- high. outputs the blanking signal for cutting the video signal of the idc display. the output is active-high. inputs the horizontal synchronizing signal of the idc display. the input must be active-low. inputs the vertical synchronizing signal of the idc display. the input must be active-low. the input signal can generate an interrupt. input of port 1c and a/d converter ? p1c 3 to p1c 1 3-bit i/o port ? adc 1 input of a 4-bit a/d converter input of a 4-bit a/d converter serial interface and input for port 0b, port 0a, horizontal synchronizing signal counter, and timer ? p0a 3 to p0a 0 4-bit i/o port. each bit can be set for input or output. ? p0b 3 to p0b 0 4-bit i/o port. each bit can be set for input or output. ? hscnt inputs the count of the horizontal synchronizing signal. the input is self- biased. ? tmin timer input. the pin inputs the commercial power to be used for the clock. ? si, so, sck input/output for the three-wire serial interface ? si: serial data input ? so: serial data output ? sck: shift clock input/output ? sda, scl input/output for the two-wire serial interface ? scl: serial clock input/output ? sda: serial data input/output n-ch open-drain cmos push-pull cmos push-pull cmos push-pull cmos push-pull n-ch open-drain (p0a 1 , p0a 0 ) cmos push-pull (other than p0a 1 or p0a 0 ) undefined input low level low level input input input input input
13 m pd17062 pin no. dip qfp (gc) symbol description output type at power-on reset int nc nc 48 55 5 6 7 8 10 12 14 22 25 37 39 40 41 42 44 56 57 interrupt input. contains the noise canceler. an interrupt can be generated at either the rising or falling edge of the input signal. no connection. the pins are not connected to the internal circuit of the device. they can be used as desired. input
14 m pd17062 1.2 equivalent circuits of the pins p0a (p0a 3 /so, p0a 2 /sck) p0b (p0b 1 , p0b 0 /si) p1b (p1b 3 , p1b 2 , p1b 1 , p1b 0 ) p1c (p1c 3 /adc 1 , p1c 2 , p1c 1 ) v dd v dd a/d converter (only for p1c/adc) reset signal (except for p1c) read instruction (only for p1c) p0a (p0a 1 /scl, p0a 0 /sda) (i/o)
15 m pd17062 p0c (p0c 3 , p0c 2 , p0c 1 , p0c 0 ) red, green, blue, blank, psc (output) pwm (pwm 3 , pwm 2 , pwm 1 , pwm 0 ) p1a (p1a 3 , p1a 2 , p1a 1 , p1a 0 ) (output) p0d (p0d 3 /adc 5 , p0d 2 /adc 4 , p0d 1 /adc 3 , p0d 0 /adc 2 ) a/d converter high on-state resistance (input) adc 0 a/d converter selection signal
16 m pd17062 p0b 3 /hscnt port horizontal synchronizing signal counter p-ch n-ch p0b 2 /tmin port timer/counter p-ch n-ch
17 m pd17062 h sync , v sync , int nc , ce (hysteresis input) x out , x in x in x out eo vco (input)
18 m pd17062 2. program memory (rom) program memory stores the program to be executed by the cpu, as well as predetermined constant data. 2.1 configuration of program memory fig. 2-1 shows the configuration of program memory. as shown in fig. 2-1, the capacity of the program memory is 8k bytes (3968 16 bits). locations in program memory are addressed in units of 16 bits. the total address range is from 0000h to 0f7fh. memory is divided into pages. the range of page 0 is from 0000h to 07ffh, while that of page 1 is from 0800h to 0f7fh. the range from 0800h to 0f7fh can be used as the crom (character rom) area in which the display patterns for the idc are stored. if this area is not used as crom, it can be used as a program area. the range from 0000h to 00ffh is a table reference area. the area is used by the jmp @ar, call @ar, movt, push, and pop instructions. fig. 2-1 configuration of program memory address program memory (rom) 16 bits page 0 page 1 (area that can be used as crom) 3968 steps 0000h 07ffh 0800h 0f7fh b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0
19 m pd17062 2.2 functions of program memory program memory has two basic functions: (1) program storage (2) constant data storage a program is a set of instructions that control the cpu (central processing unit: device that actually controls the microcontroller). the cpu executes processing sequentially according to the instructions coded in the program. the cpu sequentially reads instructions from the program stored in program memory and executes processing according to each instruction. each instruction is one word, or 16 bits in length. a single instruction can thus be stored at a single address in program memory. constant data is predetermined data such as a display pattern. constant data is read from program memory into a data buffer (dbf) in data memory (ram) upon execution of the specialized movt instruction. this reading of constant data from memory is called table referencing. program memory is read-only storage that cannot be rewritten by the execution of an instruction. in this document, program memory and rom (read-only memory) are synonymous. 2.3 program flow a program stored in program memory is usually executed one address at a time starting from address 0000h. if another program is to be executed upon some condition being satisfied, the program flow must be branched. to achieve this, the branch instruction (br) is used. if a single program is executed a number of times, the efficiency of the program memory is reduced. this problem can be solved by storing that program at a given location and calling it using the specialized call instruction. such a program is called a subroutine while the usual program is called a main routine. if a program is executed upon some condition being satisfied, independently of the current program flow, the interrupt function is used. if a predetermined condition is satisfied, the interrupt function transfers control to a specified address (vector address) irrespective of the current program flow. these program flows are controlled by the program counter (pc), which specifies program memory addresses.
20 m pd17062 2.4 branching a program a program is branched by execution of the branch instruction (br). fig. 2-2 illustrates the operation of the branch instruction. branch instructions (br) are divided into two types. direct branch instructions (br addr) transfer control to a program memory address (addr) directly specified in its operand. indirect branch instructions (br @ar) transfer control to a program memory address specified in an address register (ar), described below. see also chapter 3 . 2.4.1 direct branch a direct branch instruction uses the least significant bit of the operation code and the 11 bits of its operand, 12 bits in total, to specify the destination program memory address. the destination of the direct branch instruction can be any address in program memory between 0000h and 0f7fh. 2.4.2 indirect branch the indirect branch instruction uses the eight-bit data of an address register to specify the destination address. the destination of the indirect branch instruction is limited to addresses between 0000h and 00ffh. see section 8.1 .
21 m pd17062 fig. 2-2 operation of branch instruction and machine code (a) direct branch (br addr) (b) indirect branch (br @ar) address program memory label: instruction (machine code) page 0 page 1 0000h 0500h 07ffh 0800h 0900h 0f7fh br aaa (0c500) br bbb (0d100) aaa: bbb: br aaa (0c500) br bbb (0d100) address program memory label: instruction (machine code) page 0 page 1 0000h 0010h 0085h 0500h 07ffh 0800h 0f7fh mov ar0, #5h mov ar1, #8h br @ar mov ar0, #0h mov ar1, #1h br @ar remark the machine code (16 bits) of the 17k series consists of five blocks, of one bit, four bits, three bits, four bits, and four bits. in this document, machine code is represented in these blocks so that it can be easily understood. example machine code 0c500 ? 0 1100 101 0000 0000 14 3 4 4 2.4.3 notes on debugging direct branch instructions to page 0 (addresses 0000h to 07ffh) and page 1 (addresses 0800h to 0f7fh) use different operation codes, as shown in fig. 2-2. the operation codes of the direct branch instructions to page 0 and page 1 are 0ch, and 0dh, respectively. the difference arises because the direct branch instruction uses the addr operand, which is only 11 bits long, together with the least significant bit of the operation code, to specify the branch destination address. when assembling a program, the 17k series assembler (as17k) references a jump destination identified by a label and automatically converts the that instruction. if the program is patched during debugging, the programmer must determine whether the branch destination is on page 0 or page 1 and convert the instruction into operation code 0ch or 0dh. if address bbb in (a) of fig. 2-2 is patched from 0900h to 0910h, for example, the machine code of the br bbb instruction must be changed to 0d110.
22 m pd17062 2.5 subroutine if a subroutine is executed, the specialized subroutine call instruction (call) and subroutine return instruction (ret, retsk) are used. fig. 2-3 illustrates the operation of subroutine call. subroutine call instructions are divided into two types. the direct subroutine call instruction (call addr) calls the program memory address (addr) specified in its operand. the indirect subroutine call instruction (call @ar) calls the program memory address specified in an address register. the ret or retsk instruction is used to return control from a subroutine. the ret or retsk instruction returns control to a program memory address next to the address at which the subroutine call instruction (call) was executed. upon execution of the retsk instruction, the first instruction after the return is executed as a no-operation instruction (nop). see also chapter 3 . 2.5.1 direct subroutine call the direct subroutine call instruction uses 11 bits of its operand to specify the program memory address to be called. if the direct subroutine call instruction is used, the destination, or the first address of the subroutine to be called, must be page 0 (addresses 0000h to 07ffh). the instruction cannot call a subroutine whose first address is in page 1 (addresses 0800h to 0f7fh). the subroutine return instruction (ret, retsk) can be in page 1. the call instruction can be in page 0 or page 1. examples 1. when the subroutine return instruction is in page 0 when the first address of the subroutine is in page 0, as shown in fig. 2-4, the return address and return instruction can be in page 0 or page 1. when only the first address of the subroutine is in page 0, the call instruction can be used in either page. if the first address of the subroutine cannot be placed in page 0 because of programming restrictions, the method shown in example 2 can be used. 2. when the first address of the subroutine is in page 1 the branch instruction (br) is placed in page 0, as shown in fig. 2-4, and the desired subroutine (sub1) is called via the br instruction. 2.5.2 indirect subroutine call the indirect subroutine call instruction (call @ar) uses the 8-bit data in an address register (ar) to specify the address of a subroutine to be called. the instruction can call a subroutine from a program memory address between 0000h and 00ffh. see section 8.1 .
23 m pd17062 fig. 2-3 operation of subroutine call instruction (a) direct subroutine call (call addr) (b) indirect subroutine call (call @ar) address program memory instruction call sub1 page 0 page 1 0000h 07ffh 0800h 0f7fh call sub1 address program memory instruction page 0 page 1 0000h 0010h 0085h mov ar0, #5h mov ar1, #8h call @ar label: label: 0500h sub1: ret 07ffh 0800h 0f7fh sub2: sub3: ret mov ar0, #0h mov ar1, #1h call @ar fig. 2-4 sample uses of subroutine call instruction (a) if the subroutine return instruction is in page 1 (b) if the first address of the subroutine is in page 1 address program memory instruction call sub1 page 0 page 1 0000h 07ffh 0800h 0f7fh call sub1 address program memory instruction call sub1 page 0 page 1 0000h label: label: 0500h sub1: ret 07ffh 0800h 0f7fh sub1:br sub2 0890h sub2: call sub1 ret
24 m pd17062 2.6 table reference the table reference instruction is used to reference the constant data in program memory. if the movt dbf, @ar instruction is executed, data at the program memory address specified in an address register is placed in a data buffer (dbf). because each data item in program memory consists of 16 bits, the constant data placed in the data buffer by the movt instruction also consists of 16 bits (four words). because the address register consists of eight bits, the movt instruction can reference a program memory address between 0000h and 00ffh. when table referencing is executed, a single stack is used. see sections 8.1 and 10.3 . 2.7 notes on using the branch instruction and subroutine call instruction the 17k series assembler (as17k) detects an error if a program memory address (numeric address) is directly specified in the operand of the branch instruction (br) or subroutine call instruction (call). the assembler provides this function to minimize the number of bugs arising from program modification. examples 1. instruction causing an error ; # br 0005h ; the assembler detects the error. ; $ call 00f0h ; 2. instruction causing no error ; % loop1: ; the br or call instruction is executed for a label used in the br loop1 ; program. ; & sub1: ; call sub1 ; ; ( loop2 lab 0005h ; as a label type, 0005h is assigned to loop2. br loop2 ; ; ) br. ld. 0005h ; the numeric value of the operand is converted to a label type. ; it is recommended that this method not be used to reduce ; the number of bugs. for details, refer to the as17k users manual .
25 m pd17062 3. program counter (pc) the program counter addresses program memory or a program. it is a 12-bit binary counter. fig. 3-1 program counter pc 11 pc 9 pc 10 pc 8 pc 6 pc 7 pc 5 pc 3 pc 4 pc 2 pc 0 pc 1 12 bits priority interrupt cause vector address 1 int nc pin 4h 2 internal timer 3h 3v sync pin 2h 4 serial interface 1h normally, the program counter is incremented by 1 each time an instruction is executed. when a branch instruction or a subroutine call instruction is executed, however, the address specified in the operand field is loaded into the program counter. if a skip instruction has been executed, the address of the instruction following the skip instruction is specified, regardless of the contents of the skip instruction. if the specified address contains a skip condition, the instruction following the skip instruction is regarded as being a nop instruction. that is, the nop instruction is executed, and the address of the next instruction is specified. if an interrupt request is accepted, one of addresses 1 to 4 (depending on the cause of the interrupt) is loaded into the pc. if a power-on reset or a ce reset is performed, the program counter is reset to address 0. table 3-1 vector addresses upon interrupt occurrence
26 m pd17062 4. stack the stack is a register used to save an address returned by a program or the contents of the system register, described later, when a subroutine call occurs or an interrupt is accepted. 4.1 components the stack consists of a stack pointer (sp), which is a 4-bit binary counter, six 13-bit address stack registers (asrs), and two 3-bit interrupt stack registers. 4.2 stack pointer (sp) the stack pointer is located at address 01h in the register file, and specifies an address stack register. the contents of the stack pointer are decremented by 1 whenever a push operation (call, movt, or push instruction or interrupt acceptance) is performed, or incremented by 1 whenever a pop operation (ret, retsk, reti, movt, or pop instruction) is performed. the high-order bit of the stack pointer is always set to 0. the stack pointer can indicate any of eight different values, 0h to 7h. however, 6h and 7h are not assigned to the stack. fig. 4-1 structure of stack pointer table 4-1 behavior of stack pointer 0 (spb 2 ) (spb 1 ) (spb 0 ) msb lsb instruction stack pointer value call addr call @ar movt dbf, @ar sp C 1 push ar interrupt acceptance ret retsk movt dbf, @ar sp + 1 pop ar reti
27 m pd17062 4.3 address stack registers (asrs) there are six address stack registers, each consisting of 13 bits. after a subroutine call instruction has been executed or an interrupt request accepted, the contents of the address stack register will contain a value that is equal to the contents of the program counter, plus one, or the return address. the contents of an address stack register are loaded into the program counter by executing a return instruction, after which control returns to the original program flow. the address stack registers are used for both subroutine calls and interrupts. if two levels of the address stack registers are used for interrupts, the remaining four levels can be used for subroutine calls. if a movt instruction is executed, an address stack register is used temporarily. fig. 4-2 structure of address stack registers 4.4 interrupt stack registers there are two interrupt stack registers, each consisting of three bits, as shown in fig. 4-3. if an interrupt is accepted, the value of the two bits of the bank register (bank) and the value of the one bit of the index-enable flag (ixe) in the system register (sysreg), described later, are saved to an interrupt stack register. once an interrupt return instruction (reti) has been executed, the contents of the interrupt stack register are returned to the bank register and the index-enable flag of the system register. unlike the address stack registers, the interrupt stack registers contain no addresses specified by the stack pointer. as shown in fig. 4-4, data is saved to an interrupt stack pointer each time an interrupt is accepted, the saved data being returned whenever an interrupt return instruction is executed. if accepted interrupts consist of more than two levels, the first level of data is pushed out. thus, it must be saved by the program. if a power-on reset is performed, the contents of the interrupt stack registers become undefined. even if a ce reset is performed or a clock stop instruction is executed, however, the contents of the interrupt stack registers remain as is. asr 0 asr 1 asr 2 asr 3 asr 4 asr 5 0h 1h 2h 3h 4h 5h stack pointer value
28 m pd17062 fig. 4-3 structure of interrupt stack registers msb lsb 0h 1h banksk0 banksk1 ixesk0 ixesk1 fig. 4-4 behavior of interrupt stack registers not defined b a not defined a not defined a not defined not defined not defined reti reti interrupt b interrupt a v dd is applied.
29 m pd17062 5. data memory (ram) data memory is used to store data for operations and control. simply by executing an appropriate instruction, data can be written to and read from data memory at any time. 5.1 structure of data memory fig. 5-1 shows the structure of data memory. as shown in fig. 5-1, data memory is divided into three units called banks. these three banks are called bank0, bank1, and bank2. in each bank, data is assigned an address in units of four bits. the high-order three bits are called the row address, while the low-order four bits are called the column address. for example, the data memory location having row address 1h and column address ah is referred to as the data memory location having address 1ah. one address consists of four bits of memory. these four bits are called a nibble. data memory is divided into the blocks described in sections 5.1.1 to 5.1.5 , according to function.
30 m pd17062 fig. 5-1 data memory structure 0123456789 abcdef 0 1 2 3 4 5 6 7 dbf3 dbf2 dbf1 dbf0 p0a (4 bits) system register p0b (4 bits) p0c (4 bits) p0d (4 bits) bank0 0123456789 abcdef 0 1 2 3 4 5 6 7 p1a (4 bits) system register p1b (4 bits) p1c (4 bits) fixed at 0 bank1 0123456789 abcdef 0 1 2 3 4 5 6 7 p0a (4 bits) system register p0b (4 bits) p0c (4 bits) p0d (4 bits) bank2 the same register is allocated for each bank.
31 m pd17062 5.1.1 structure of the system register (sysreg) the system register consists of 12 nibbles, located at addresses 74h to 7fh in data memory. the system register is allocated regardless of the bank. that is, the system register is always located at addresses 74h to 7fh, regardless of the bank. fig. 5-2 shows the structure. fig. 5-2 structure of the system register 5.1.2 structure of the data buffer (dbf) the data buffer consists of four nibbles located at addresses 0ch to 0fh of bank0 in data memory. fig. 5-3 shows the structure. fig. 5-3 structure of the data buffer 74h 75h 76h 77h 78h 79h 7ah 7bh 7ch 7dh 7eh 7fh address program status word (psword) system register (sysreg) register (symbol) address register (ar) window register (wr) bank register (bank) index register (ix) data memory row address pointer (mp) general-purpose register pointer (rp) 0ch dbf3 0dh dbf2 0eh dbf1 0fh dbf0 data buffer (dbf) address symbol
32 m pd17062 5.1.3 structure of the general-purpose register (gr) the general-purpose register consists of 12 nibbles, specified with an arbitrary row address, in data memory. an arbitrary row address is specified using the general-purpose register pointer in the system register. fig. 5-4 shows the structure. fig. 5-4 structure of the general-purpose register (gr) sysreg 0 1 2 3 4 5 6 7 sysreg 0 1 2 3 4 5 6 7 row address 0123456789abcdef column address bank0 bank1 general-purpose register the same register is allocated for each bank. area specifiable as general-purpose register pointed to by general-purpose register pointer (rp) in system register. sysreg 0 1 2 3 4 5 6 7 bank2
33 m pd17062 5.1.4 structure of port data registers (port register) the port registers consist of 12 nibbles at addresses 70h to 73h of the banks of data memory. fig. 5-5 shows the structure of the port registers. as shown in fig. 5-5, the same port registers are allocated in bank0 and bank2. thus, the port registers actually consist of eight nibbles. fig. 5-5 structure of port registers 5.1.5 structure of general-purpose data memory general-purpose data memory consists of that part of memory other than the system register and the port registers of data memory. general-purpose data memory consists of a total of 336 words, with 112 words in each of bank0 to bank2. 5.1.6 unmounted data memory as shown in fig. 5-6, nothing is assigned to bit 0 of address 72h in bank1 of the port registers. for an explanation of this address, see section 5.3.2 . 70h 71h 72h 73h p0a p0b p0c p0d p1a p1b p1c fixed at 0 bank0 bank2 bank1 port register address symbol
34 m pd17062 5.2 functions of data memory data memory can be used to perform, with one instruction, a four-bit operation, comparison, decision, or transfer of the data in data memory and immediate data (arbitrary data) by executing one of the data memory manipulation instructions listed in table 5-1. if the general-purpose register is used, a four-bit operation, comparison, or transfer between data memory and the general-purpose register can be performed by a single instruction. examples are given below. see chapters 6 and 7 for details. example 1. operation on data in data memory ; # mov 35h, #0001b ; transfer (write) immediate data 0001b to data ; memory address 35h in the currently selected bank. ; $ add 76h, #0001b ; add immediate data 0001b to the contents of ; data memory address 76h in the currently selected ;bank. in instructions # and $ , the currently selected bank is specified in the bank register of the system register. for an explanation of the bank register, see chapter 8 . in $ , the instruction is for addition to the contents of data memory address 76h. address 76h is part of the system register. because the system register always exists regardless of the bank, the add instruction eventually adds 0001b to the contents of address 76h of the system register, regardless of the bank. remark for explanation of how to code instructions, see section 5.3.1 . example 2. operation between data memory and the general-purpose register assume that the general-purpose register is allocated to row address 1h of bank0. ; # add 7h, 36h ; add the contents of data memory address 36h in the ; currently selected bank to the contents of the ; general-purpose register location having column address ; 7h, or address 17h of bank0. ; $ ld 7h, 36h ; transfer the contents of data memory address 36h to ; the general-purpose register location having column ; address 7h. ; in this instruction, the general-purpose register ; location is address 17h of bank0. the system register, data buffer, general-purpose register, and port registers can be manipulated in the same way as data memory by using the data memory manipulation instructions. sections 5.2.1 to 5.2.4 describe the functions of these registers.
35 m pd17062 5.2.1 function of system register (sysreg) the system register is used to control the cpu. for example, the bank register shown in fig. 5-2 is used to specify a data memory bank, while the general- purpose register pointer specifies the row address of the general-purpose register. see chapter 8 for details. 5.2.2 function of general-purpose register (gr) the general-purpose register can be used both to perform operations on the data in data memory and to transfer data to and from data memory. the bank and the row address for the general-purpose register are specified by the general-purpose register pointer in the system register. the general-purpose register pointer of the m pd17062 always specifies bank0. for example, if the general-purpose register pointer is set to 0, 16 nibbles at row address 0 of bank0, or addresses 00h to 0fh of bank0, are allocated as the general-purpose register. note that if the general-purpose register is used, transfer and arithmetic/logical instructions that involve the general-purpose register and immediate data cannot be executed. that is, the execution of a transfer or an arithmetic/logical instruction that involves the general-purpose register and immediate data requires that the general-purpose register be treated as data memory. for example, assume that row address 0h of bank0 is allocated as the general-purpose register (i.e., the value of the general-purpose register pointer is 0). in this case, if the currently selected bank is bank0 (i.e., the value of the bank register is 0), executing add 00h, #1 increments by 1 the contents of address 00h of bank0, which is allocated as the general register. however, if the currently selected bank is bank1 (i.e., the value of the bank register is 1), executing add 00h, #1 increments by 1 the contents of address 00h of bank1. see chapter 6 for details. 5.2.3 data buffer (dbf) the data buffer is used to store data to be transferred to a peripheral circuit, such as the reference voltage setting data for an a/d converter. it is also used to store data transferred from a peripheral circuit, such as input data for a serial interface. see chapter 10 for details. 5.2.4 general-purpose port data registers (port registers) port registers are used both to store output data for general-purpose i/o ports and to read input data. the output of the pins assigned as an output port is determined by storing data into the port registers that correspond to those pins. the input status of those pins assigned as an input port can be detected by reading the contents of the port registers corresponding to those pins. fig. 5-6 shows the correspondence between the port registers and ports (pins). see chapter 15 for details.
36 m pd17062 table 5-1 data memory manipulation instructions function instruction add addc sub subc and or xor ske skge sklt skne mov ld st skt skf addition subtraction logical operation operation comparison transfer decision
37 m pd17062 fig. 5-6 correspondence between port registers and ports (pins) 70h p0a 71h p0b 72h p0c 73h p0d 70h p1a 71h p1b 72h p1c 73h fixed at 0 b 3 p0a3 b 2 p0a2 b 1 p0a1 b 0 p0a0 b 3 p0b3 b 2 p0b2 b 1 p0b1 b 0 p0b0 b 3 p0c3 b 2 p0c2 b 1 p0c1 b 0 p0c0 b 3 p0d3 b 2 p0d2 b 1 p0d1 b 0 p0d0 b 3 p1a3 b 2 p1a2 b 1 p1a1 b 0 p1a0 b 3 p1b3 b 2 p1b2 b 1 p1b1 b 0 p1b0 b 3 p1c3 b 2 p1c2 b 1 p1c1 b 0 p1c0 port0a port0b port0c port0d port1a port1b port1c p0a 3 p0a 2 p0a 1 p0a 0 p0b 3 p0b 2 p0b 1 p0b 0 p0c 3 p0c 2 p0c 1 p0c 0 p0d 3 p0d 2 p0d 1 p0d 0 p1a 3 p1a 2 p1a 1 p1a 0 p1b 3 p1b 2 p1b 1 p1b 0 p1c 3 p1c 2 p1c 1 general-purpose port data register address bank symbol bit symbol corresponding port pin symbol input or output bank0 bank2 bank1 input and output (group i/o) output input input and output (bit i/o) output input and output (bit i/o) input and output (bit i/o)
38 m pd17062 5.3 notes on using data memory 5.3.1 addressing data memory if the 17k series assembler is being used and a numeric representing a data memory address is specified directly in an operand of a data memory manipulation instruction, as shown in example 1, an error will occur. this error occurs to facilitate the maintainability of programs and to reduce the number of causes of bugs when a program is modified. in this data sheet, however, real-address notation is used in the sample programs to make them easy to understand. when coding an actual program, refer to the assembler instruction manual. example 1. instructions that result in an error ; # mov 2fh, #0001b ; address 2fh is specified directly. ; $ mov 0.2fh, #0001b ; address 2fh in bank0 is specified directly. instructions that do not cause an error ; % m02f mem 0.2fh ; address 2fh of bank0 is defined symbolically in mov m02f, #0001b ; m02f as a memory-type address. ; & mov .md.2fh, #0001b ; address 2fh is converted into a memory-type ; address by using .md.. however, the use of this type of ; instruction should be avoided to reduce the ; likelihood of bugs arising. using an assembler pseudo instruction, namely the mem instruction (symbol definition pseudo instruc- tion), symbolically define a data memory address in advance. if a data memory address is defined symbolically, a data memory bank must also be specified, as shown in example 2. this data memory bank specification is used when a data memory map is automatically created in the assembler. note that if a symbolically defined data memory address for bank2 is used in the range of bank1 in a program, as shown in example 2, the operation is performed in bank1 data memory.
39 m pd17062 example 2. 5.3.2 notes on using unmounted data memory as shown in fig. 5-6, nothing is actually assigned to bit 0 (lsb) of address 72h of bank1 of the port registers. if a data memory manipulation instruction is executed for this address, the following operations are performed: (1) device behavior if a read instruction is executed, a 0 is read. executing a write instruction results in no change. (2) assembler behavior normal assembly is performed. no error occurs. (3) emulator (ie-17k) behavior if a read instruction is executed, a 0 is read. executing a write instruction results in no change. no error occurs. m1 m2 m3 mem mem mem 0.15h 1.15h 2.15h ; ; ; bank row address column address bank1 mov m1, mov m2, mov m3, #0000b #0000b #0000b ; ; ; ; assembler built-in macro instruction bank ? 1 m1, m2, and m3 are defined symbolically in # for different banks, but are for bank1 in this program. thus, all of these three instructions write 0s to data memory address 15h in bank1. symbol definition pseudo instruction
40 m pd17062 6. general-purpose register (gr) the general-purpose register is allocated in data memory space, and is used to perform direct operations on the data in data memory and to transfer data to and from data memory. 6.1 structure of the general-purpose register fig. 6-1 shows the structure of the general-purpose register. as shown in fig. 6-1, 16 words (16 words 4 bits) having the same row address in data memory space can be used as the general-purpose register. the row address to be used as the general-purpose register can be specified using the general-purpose register pointer of the system register. the general-purpose register consists of seven bits. however, the high-order four bits are fixed to 0 so, within the data memory space, only row addresses 0h to 7h of bank0 can be used as the general-purpose register. see section 8.6 . 6.2 function of the general-purpose register the general-purpose register can be used to perform an operation or to transfer data between itself and data memory with the execution of a single instruction. the general-purpose register is allocated in data memory space. this enables an operation or transfer to be performed between data memory locations by the execution of a single instruction. like other data memory, the general-purpose register can be controlled using a data memory manipulation instruction.
41 m pd17062 fig. 6-1 structure of general-purpose register rph rpl 7dh 7eh b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 0000b 2 b 1 b 0 b c d (rp) 0123456789abcdef 0 2 3 4 5 6 7 1 0 2 3 4 5 6 7 1 0 2 3 4 5 6 7 1 column address row addresses 0h to 7h of bank0 can be freely specified using the general- purpose register pointer (rp). row address general-purpose register (16 words) general-purpose register allocated when rp = 010b. system register rp bank0 system register bank1 the same system register is viewed. system register bank2 general-purpose register pointer (rp) symbol address bit function
42 m pd17062 6.3 address generation for general-purpose register and data memory in individual instructions table 6-1 lists the operation and transfer instructions that can be executed for the data in the general- purpose register and data memory. consider the following instruction: add r, m ((r) ? (r) + (m)) upon executing this instruction, the address of the general-purpose register is generated from the value of the general-purpose register pointer and the value specified in r, as shown in table 6-2. then, the contents of the general-purpose register specified by the generated address of the general-purpose register are added to the contents of the data memory location specified in m, the result being stored into the general-purpose register. the address of the general-purpose register is generated, as described above, for each of the instructions listed in table 6-1. table 6-1 manipulation instructions executed between the general-purpose register and data memory table 6-2 address generation for general-purpose register and data memory data memory address specified in m instruction address generated address bank row address column address general-purpose register address specified in r add r, m (0000b) (bank) (00 b) m (rp) r instruction set instruction operation addition add r, m (r) ? (r) + (m) addc r, m (r) ? (r) + (m) + cy subtraction sub r, m (r) ? (r) C (m) subc r, m (r) ? (r) C (m) C cy logical operation and r, m (r) ? (r) (m) or r, m (r) ? (r) (m) xor r, m (r) ? (r) - (m) transfer ld r, m (r) ? (m) st m, r (m) ? (r) mov @r, m if mpe = 1: (mp, (r)) ? (m) if mpe = 0: (bank, m r , (r)) ? (m) mov m, @r if mpe = 1: (m) ? (mp, (r)) if mpe = 0: (m) ? (bank, m r , (r)) shift rorc r right shift, including a carry
43 m pd17062 example 1. when bank0 is selected and rpl, #0001b ; rp ? 0000000b; the general-purpose register is allocated in row ; address 0h in bank0. add 04h, 56h ; executing the above instruction adds the contents of address 04h of bank0, part of the general-purpose register, to the contents of data memory address 56h, then stores the result into address 04h of the general- purpose register. see fig. 6-2. fig. 6-2 execution of instructions in example 1 0123456789abcdef 0 2 3 4 5 6 7 1 m rp 0000000b bank0 add 04h, 56h system register column address general-purpose register row address
44 m pd17062 example 2. when bank0 is selected and mpe = 0 is specified mov 04h, #8 ; 04h ? 8 and rpl, #0001b ; rp ? 0000000b; the general-purpose register is allocated in row ; address 0h in bank0. mov @04h, 52h executing the above instruction transfers the contents of data memory address 52h to address 58h. the mov @r, m instruction is called an indirect transfer of the general-purpose register contents. in this instruction, the contents of the general-purpose register address specified in r (8 in the above example) consist of the column address of data memory, and the row address specified in m (5 in the above example) is the row address of data memory. that is, the data memory address is 58h (see fig. 6-3 ). see section 8.5 for an explanation of the indirect transfer of the general-purpose register contents. fig. 6-3 execution of instructions in example 2 example 3. and rpl, #0000b ; rp ? 0000000b; the general-purpose register is allocated in row ; address 0h of bank0. mov bank, #0010b ; bank2 ld 01h, 31h ld 02h, 32h ld 03h, 33h ld 04h, 34h or rpl, #1000b ; rp ? 0000100b; the general-purpose register is allocated in row ; address 4h of bank0. ld 05h, 45h ld 06h, 46h ld 07h, 47h ld 08h, 48h 0123456789abcdef 0 2 3 4 5 6 7 1 rp bank0 mov m @ 04h, 56h 8 system register column address general-purpose register row address
45 m pd17062 example 3 shows a program that transfers eight words of data from bank2 to bank0 data memory in units of four words, as shown in fig. 6-4. if the general-purpose register is allocated in a fixed row address, for example, only in row address 0 of bank0, instructions are needed to transfer all of the eight words to the register and then store them into data memory. in contrast, if the row address of the general-purpose register is changed using the general-purpose register pointer as shown in example 3, the operation can be completed simply by executing a storage instruction. fig. 6-4 execution of instructions in example 3 0123456789abcdef 0 2 3 4 5 6 7 1 rp bank0 0 2 3 4 5 6 7 1 bank1 0 2 3 4 5 6 7 1 bank2 rp = 0000000b rp = 0000100b system register column address row address system register system register
46 m pd17062 6.4 notes on using the general-purpose register this section provides notes on using the general-purpose register, referring to the following example: example and rpl, #000b ; rp ? 0000010b or rpl, #0100b ; mov bank, #0000b ; bank0 ld 04h, 32h executing the above instructions loads the contents of address 32h of bank0 data memory into address 24h in the general-purpose register of bank0. in the above example, the general-purpose register is allocated in row address 2h of bank0, so that the address of the general-purpose register specified in r in instruction ld r, m is address 24h of bank0. the data memory address specified in m is address 32h of bank0. (see fig. 6-5 .) note that it is necessary to code an actual data memory address, for example, 24h, as the value specified in r when using the assembler. in this case, only the low-order four bits are needed as the value for r, so the assembler ignores value 2h, which is a row address. thus, executing instruction ld 24h, 32h produces the same result as executing the instruction in the above example. if, when using the assembler, the address of the general-purpose register is specified directly in an operand of an instruction, as shown below, an error occurs. instruction that causes an error ld 04h, 32h ; the address of the general-purpose register is coded as 04. most commonly used method r1 mem 0.04h ; m1 mem 0.32h ; # r1 and m1 are defined as memory-type addresses, and are ld r1, m1 ; assigned addresses 04h and 32h of bank0, respectively. executing the following instructions produces the same result as executing the instructions in # because r1 and r2 are assigned the same column address. r2 mem 0.34h m1 mem 0.32h ld r2, m1
47 m pd17062 fig. 6-5 execution of the above example also, note the following when the general-purpose register is being used. no arithmetic/logical instructions are provided for the general-purpose register and immediate data. that is, the execution of an arithmetic/ logical instruction that involves data memory allocated as the general-purpose register and immediate data requires that the data memory be treated as data memory rather than the general-purpose register. 0123456789abcdef 0 2 3 4 5 6 7 1 rp bank0 rp = 0000010b ld 04h, 32h system register column address general-purpose register row address
48 m pd17062 7. arithmetic logic unit (alu) block 7.1 overview fig. 7-1 is an overview of the alu block. as shown in fig. 7-1, the alu block consists of the alu, temporary storage registers a and b, program status word, decimal conversion circuit, and data memory address controller. the alu performs arithmetic and logic operations on the 4-bit data in the data memory and performs discrimination, comparison, rotation, and transfer. fig. 7-1 overview of the alu block data memory data bus program status word address controller temporary storage register a temporary storage register b indexing memory pointer detecting a carry, borrow, or zero setting decimal calculation or result storage alu ? arithmetic operation ? logic operation ? bit discrimination ? comparative discrimination ? rotation ? transfer decimal conversion
49 m pd17062 7.2 configuration and functions of the components of the alu block 7.2.1 alu in response to a programmed instruction, the alu performs 4-bit arithmetic or logic processing, bit discrimination, comparative discrimination, rotation, or transfer. 7.2.2 temporary storage registers a and b temporary storage registers a and b temporarily hold the 4-bit data. these registers are automatically used when an instruction is executed. they cannot be controlled by a program. 7.2.3 program status word a program status word controls the operation of the alu and holds the status of the alu. for details of the program status word, see section 8.7 . 7.2.4 decimal conversion circuit if the bcd flag of the program status word is set to 1 when an arithmetic operation is executed, the decimal conversion circuit converts the results of the arithmetic operation to a decimal number. 7.2.5 address controller the address controller specifies an address in data memory. at the same time, the circuit also controls address modification by the index register or data memory row address pointer. 7.3 alu operations table 7-1 lists the operations performed by the alu when instructions are executed. table 7-2 shows the data memory address modification by the index register and data memory row address pointer. table 7-3 lists the converted decimal data used in decimal operations.
50 m pd17062 table 7-1 alu operations alu function addition subtraction logic operation discrimi- nation comparison transfer rotation add addc sub subc or and xor skt skf ske skne skge sklt ld st mov rorc r r, m m, #n4 r, m m, #n4 r, m m, #n4 r, m m, #n4 r, m m, #n4 r, m m, #n4 r, m m, #n4 m, #n m, #n m, #n4 m, #n4 m, #n4 m, #n4 r, m m, r m, #n4 @r, m m, @r 00 01 10 11 instruction operation difference due to program status word (psword) address modification value of the bcd flag value of the cmp flag operation operation of the cy flag operation of the z flag index memory pointer optional (hold) optional (hold) optional (hold) optional (hold) optional (hold) optional (hold) optional (hold) optional (hold) optional (hold) optional (reset) binary operation the result is stored. binary operation the result is not stored. decimal operation the result is stored. decimal operation the result is not stored. not changed not changed not changed not changed not changed set by a carry or borrow. otherwise, the flag is reset. retains the previous state. retains the previous state. retains the previous state. retains the previous state. retains the previous state. retains the previous state. retains the previous state. retains the previous state. value of b 0 of the general- purpose register retains the previous state. set if the operation result is 0000b. otherwise, the flag is reset. set if the operation result is 0000b. otherwise, the flag is reset. retains the status if the operation result is 0000b. otherwise, the flag is reset. retains the status if the operation result is 0000b. otherwise, the flag is reset. provided not provided provided not provided provided not provided provided provided not provided not provided provided not provided not provided
51 m pd17062 table 7-2 modification of the data memory address and indirect transfer address by the index register and data memory row address pointer bank : bank register ix : index register ixe : index enable flag ixh : bits 10 to 8 of the index register ixm : bits 7 to 4 of the index register ixl : bits 3 to 0 of the index register m : data memory address specified with m r and m c m r : data memory row address (high order) m c : data memory column address (low order) mp : data memory row address pointer mpe : memory pointer enable flag r : general-purpose register column address rp : general-purpose register pointer ( ) : contents addressed by b 3 b 2 b 1 b 0 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 2 b 1 b 0 b 3 b 2 b 1 b 0 ixe mpe 00 01 10 11 rp r bank m bank m r (r) (r) mp bank m bank m r (r) mp (r) ixh, ixm ix logical or general-purpose register address specified with r data memory address specified with m indirect transfer address specified with @r bank row address column address bank row address column address bank row address column address same as above same as above same as above same as above same as above logical or
52 m pd17062 table 7-3 converted decimal data remark correct decimal conversion is not possible in the shaded area. operation result hexadecimal addi- tion 0 0 0000b 0 0000b 1 0 0001b 0 0001b 2 0 0010b 0 0010b 3 0 0011b 0 0011b 4 0 0100b 0 0100b 5 0 0101b 0 0101b 6 0 0110b 0 0110b 7 0 0111b 0 0111b 8 0 1000b 0 1000b 9 0 1001b 0 1001b 10 0 1010b 1 0000b 11 0 1011b 1 0001b 12 0 1100b 1 0010b 13 0 1101b 1 0011b 14 0 1110b 1 0100b 15 0 1111b 1 0101b 16 1 0000b 1 0110b 17 1 0001b 1 0111b 18 1 0010b 1 1000b 19 1 0011b 1 1001b 20 1 0100b 1 1110b 21 1 0101b 1 1111b 22 1 0110b 1 1100b 23 1 0111b 1 1101b 24 1 1000b 1 1110b 25 1 1001b 1 1111b 26 1 1010b 1 1100b 27 1 1011b 1 1101b 28 1 1100b 1 1010b 29 1 1101b 1 1011b 30 1 1110b 1 1100b 31 1 1111b 1 1101b operation result decimal addition cy cy operation result 0 0 0000b 0 0000b 1 0 0001b 0 0001b 2 0 0010b 0 0010b 3 0 0011b 0 0011b 4 0 0100b 0 0100b 5 0 0101b 0 0101b 6 0 0110b 0 0110b 7 0 0111b 0 0111b 8 0 1000b 0 1000b 9 0 1001b 0 1001b 10 0 1010b 1 1100b 11 0 1011b 1 1101b 12 0 1100b 1 1110b 13 0 1101b 1 1111b 14 0 1110b 1 1100b 15 0 1111b 1 1101b C16 1 0000b 1 1110b C15 1 0001b 1 1111b C14 1 0010b 1 1100b C13 1 0011b 1 1101b C12 1 0100b 1 1110b C11 1 0101b 1 1111b C10 1 0110b 1 0000b C9 1 0111b 1 0001b C8 1 1000b 1 0010b C7 1 1001b 1 0011b C6 1 1010b 1 0100b C5 1 1011b 1 0101b C4 1 1100b 1 0110b C3 1 1101b 1 0111b C2 1 1110b 1 1000b C1 1 1111b 1 1001b operation result hexadecimal subtrac- tion operation result decimal subtraction cy cy operation result
53 m pd17062 7.4 notes on using the alu 7.4.1 notes on using the program status word for operations after an arithmetic operation has been performed on the program status word, the operation result is held in the program status word. the cy and z flags of the program status word are usually set or reset according to the result of the arithmetic operation. if the arithmetic operation is performed on the program status word itself, the result of the operation is stored and a carry, borrow, or zero cannot be discriminated. if the cmp flag is set, the result of the arithmetic operation is not stored and the cy and z flags are set or reset as usual. 7.4.2 notes on performing decimal operations a decimal operation can be carried out only when the operation result is within the following ranges: (1) the result of addition is between 0 and 19 in decimal. (2) the result of subtraction is between 0 and 9 or C10 and C1 in decimal. if a decimal operation exceeding the above ranges is performed, the cy flag is set, resulting in a value greater than or equal to 1010b (0ah).
54 m pd17062 8. system register (sysreg) system register is the generic name for those registers directly related to cpu control. system registers are allocated at addresses 74h-7fh in data memory and can be referenced regardless of the bank specification. the system register types are as follows: address register window register bank register memory pointer enable flag index register data memory row address pointer general-purpose register pointer program status word fig. 8-1 configuration of system register b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 ar3 ar2 ar1 ar0 wr bank ixh ixm mph mpl ixl rph rpl psw 74h 75h 76h 77h 78h 79h 7ah 7bh 7ch 7dh 7eh 7fh 00000000 00 p0000 0000 b c d c m p c y zi x e (ix) address register symbol bit data address register (ar) system register window register (wr) bank register (bank) index register (ix) data memory row address pointer (mp) general- purpose register pointer (rp) program status word (psword) m e (mp)
55 m pd17062 b 3 0 b 2 0 b 1 0 b 0 0 b 3 0 b 2 0 b 1 0 b 0 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 ar 15 (msb) ar 0 (lsb) ar0 (77h) ar1 (76h) ar2 (75h) ar3 (74h) 8.1 address register (ar) the address register specifies a program memory address. it is located at addresses 74h-77h. the instructions used to manipulate the address register are indirect branch instructions (br @ar, call @ar), the table reference instruction (movt), and stack manipulation instructions (push, pop). an indirect branch is a branch to the program memory address specified by the contents of the address register. indirect branch instructions include br @ar and call @ar. table reference is the transfer of the contents of the program memory address specified by the address register to the dbf of data memory (bank0 0dh-0fh). this is done by executing a movt instruction. stacks are manipulated using the push and pop instructions. the push instruction stores the contents of the address register in the stack specified by the current stack pointer, and decrements the contents of the stack pointer by 1. the pop instruction increments the contents of the stack pointer by 1, and loads the contents of the stack specified by the current stack pointer into the address register. ar3 and ar2 of m pd17062 are fixed at 0. hence, the program address that can be specified by the address register is the 256 steps of 0000h-00ffh. fig. 8-2 configuration of address register 8.2 window register (wr) the window register is a 4-bit register, mapped to address 78h of the system register. it is used for data transfer together with the register file (rf), described later in this manual. all data in each register of the register file is manipulated via the window register. data transfer between the window register and the register file is achieved by execution of the exclusive peek wr, rf and poke rf, wr instructions.
56 m pd17062 8.3 bank register (bank) the bank register specifies a data memory bank. the bank register contains bank0 upon reset. the two high-order bits of address 79h are consistently set to 0. data memory is classified into three banks by the bank register. when a data memory manipulation instruction is executed, it acts on the data memory in the bank specified by the bank register. for example, to manipulate bank1 data memory with bank0 set as the current bank, the bank must first be switched to bank1 in the bank register. however, system registers allocated to addresses 74h-7fh of data memory are not confined to the concept of banks. the same system registers exist at addresses 74h-7fh of all banks. executing mov 78h, #0 in bank1 and mov 78h, #0 in bank2 both result in writing 0 to address 78h of the system register. therefore, system register manipulation is not constrained to the concept of banks. when an interrupt is accepted, bank is saved. table 8-1 specification of data memory bank 8.4 memory pointer enable flag (mpe) the mpe specifies whether to specify the row address for execution of the mov @r, m and mov m, @r instructions by the mpl, or to perform execution with the same address. when the mpe is set, the row address is specified by the mpl. when the mpe is reset, the instruction is executed with same row address. however, the address specified by the mpl is the row address of the currently specified bank. bank request data memory bank (bank) b 3 b 2 b 1 b 0 0 0 0 0 bank0 0 0 0 1 bank1 0 0 1 0 bank2 0 0 1 1 not to be set
57 m pd17062 8.5 index register (ix) and data memory row address pointer (mp) 8.5.1 configuration of index register and data memory row address pointer as shown in fig. 8-1, the index register consists of 11 bits, including the three low-order bits, of 7ah (ixh) of the system register, 7bh, and 7ch (ixm, ixl). the index register is used to indirectly specify a data memory address. the data memory row address pointer consists of 7 bits, including the three low-order bits of 7ah (mph) and 7bh (mpl). this means that the seven high-order bits of the index register and data memory row address pointer are shared. the four high-order bits of the index register, i.e., the four high-order bits of the data memory row address pointer (7ah b 2 -b 0 , 7bh b 3 ), of m pd17062 are fixed at 0.
58 m pd17062 8.5.2 functions of index register and data memory row address pointer when a data memory manipulation instruction is executed with the index enable flag (ixe) set to 1, the index register ors the data memory bank/address specified by the instruction and the contents of the index register. then, the index register executes the instruction in the data memory address indicated by the operation result (in other words, the real address). when a general-purpose register indirect transfer instruction (mov @r, m and mov m, @r) is executed with the memory pointer enable flag set to 1, the data memory row address pointer executes the instruction, regarding the indirect address bank specified by the general-purpose register and row address as being the value of the data memory row address pointer. table 8-2 shows the modification of data memory and the indirect address by the index register and data memory row address pointer. all data memories are subject to modification by the index register and data memory row address pointer. the following instructions are not subject to modification by the index register. inc ar inc ix movt dbf, @ar push ar pop ar peek wr, rf poke rf, wr get dbf, p put p, dbf br addr br @ar rorc r call addr call @ar ret retsk reti ei di stop 0 halt h nop
59 m pd17062 table 8-2 modification of data memory address by index register and data memory row address pointer m ; data memory address bank ; bank register (m) ; contents of data memory address (bank) ; contents of bank register m ; data memory address excluding banks ix ; index register m r ; data memory row address (ix) ; contents of index register r ; general-purpose register address ixh ; bits b 10 -b 8 of index register (r) ; contents of general-purpose register address ixm ; bits b 7 -b 4 of index register r ; general-purpose register column address ixl ; bits b 3 -b 0 of index register rp ; general-purpose register pointer mp ; data memory row address pointer (rp) ; contents of general-purpose register address (mp) ; contents of data memory row address pointer b 3 b 2 b 1 b 0 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 2 b 1 b 0 b 3 b 2 b 1 b 0 ixe mpe 00 01 10 11 (rp) r (bank) m (bank) m r (r) (mp) (r) bank r (bank) m r (mp) (r) logical or (ixh) (r) or logical (ix) add addc sub subc and or xor ske skge sklt skne skt skf ld st mov m m, #n4 rm m, #n4 m, #n4 m, #n m, #n4 rm @ r m general-purpose register address specified by r r data memory address specified by m m indirect transfer address specified by @r @r row address column address bank row address column address bank row address column address bank address-modified instructions addition/subtraction logical operation comparison discrimi- nation transfer same as above same as above same as above same as above same as above indirect transfer address m (ixm)
60 m pd17062 8.5.3 for mpe = 0 and ixe = 0 (data memory not modified) as shown in table 8-2, data memory addresses are not affected by the index register or data memory row address pointer. example 1. when the row address of the general-purpose register is 0 for bank0 add 03h, 11h when the above instruction is executed, the contents of general-purpose register 03h and data memory 11h are added and the result is stored in general-purpose register 03h. (see example 1 in fig. 8-3 ). example 2. when the row address of the general-purpose register is 0 for bank0 mov 05h, #8 ; 05h ? 8 mov @05h, 34h ; register indirect transfer when the above instruction is executed, the contents of the data memory at address 34h are transferred to address 38h. this means that the mov @ r, m instruction transfers the contents of data memory m to the same row address (in the above case, 3) as m and the column address (in the above case, 38h) specified by the contents (in the above case, 8) of general-purpose register r. (see example 2 in fig. 8-3 ). example 3. when the row address of the general-purpose register is 0 for bank0 mov 0bh, #0eh ; 0bh ? 0eh mov 34h @0bh ; register indirect transfer when the above instruction is executed, the contents of the data memory are transferred from address 3eh to 34h. this means that the mov m, @r instruction transfers the contents at the same row address (in the above case, 3) as data memory m and at the column address (in the above case, 3eh) specified by the contents (in the above case, 0eh) of general-purpose register r to m (see example 3 in fig. 8-3 ). the (transfer) source and (transfer) destination are exactly opposite to those in example 2.
61 m pd17062 fig. 8-3 indirect transfer of general-purpose register with mpe = 0 and ixe = 0 address generation of example 2 r m 0 0 0 0 3 3 5 4 8 (@ r) @ r, m mov 05h 34h 01 2 3 45 6 7 89 ab cde f 8e 0 1 2 3 4 5 6 7 column address row address example 1. add03h,11h specifies the destination column address specifies the source column address general- purpose register example 2. mov @05h, 34h example 3. mov 34h, @0bh bank row address column address contents of r same as m
62 m pd17062 8.5.4 for mpe = 1 and ixe = 0 (diagonal indirect transfer) as shown in table 8-2, the bank and row address of the data memory address in the indirect side specified by the general-purpose register are set to the value of the data memory row address pointer only when a general-purpose register indirect transfer instruction is executed. example 1. when the row address of the general-purpose register is 0 for bank0 mov mpl, #0101b ; mp ? 00101b mov mph, #1000b ; mpe ? 1 mov 05h, #8 ; 05h ? 8 mov @05h, 34h ; register indirect transfer when the above instruction is executed, the contents of the data memory at address 34h are transferred to address 58h of data memory. this means that the mov @r, m instruction at mpe = 1 transfers the contents of data memory m to the data memory whose bank and row addresses are the values of the data memory row address pointer (in the above example, bank0, row address 5) and whose column address is specified (in the above case, 58h of bank0) by general-purpose register r (in the above case, 8). (see example 1 in fig. 8-4 .) compared to mpe = 0 ( example 2 in section 8.5.3 ), the bank and row address of the data memory address in the indirect side specified by the general-purpose register can be specified by the data memory row address pointer (in example 2 of section 8.5.3 , the bank and row address in the indirect side are the same as those of m). therefore, specifying mpe = 1 enables general-purpose register diagonal indirect transfer to be performed. similarly, the mov m, @r instruction becomes as shown in example 2. example 2. when the row address of the general-purpose register is 0 for bank0 mov mpl, #0101b ; mp ? 00101b mov mph, #1000b ; mpe ? 1 mov 0bh, #0eh ; 0bh ? 0eh mov 3ah, @05h (see example 2 in fig. 8-4 .)
63 m pd17062 fig. 8-4 indirect transfer of general-purpose register with mpe = 1 and ixe = 0 address generation of example 1 r m 0 0 0 0 0 0 0 3 1 0 1 5 4 8 (@ r) @ r, m mov 05h 34h 01 2 3 45 6 7 89 ab cde f 8e 0 1 2 3 4 5 6 7 mp = 00101b column address specifies the destination column address specifies the source column address general- purpose register example 1. mov @05h, 34h bank row address column address contents of r value of mp example 2. mov 3ah, @0bh the bank and row address are set to 000101b, the value of the data memory row address pointer.
64 m pd17062 8.5.5 for mpe = 0 and ixe = 1 (index modification) as shown in table 8-2, when a data memory manipulation instruction is executed, the bank and row address of the data memory specified directly by the instruction are ored with the index register. then, the instruction is executed in the data memory address specified by the operation result (real address). example 1. when the row address of the general-purpose register is 0 for bank0 mov ixl, #0010b ; ix ? 000000010b mov ixm, #0000b ; mpe ? 0 mov ixh, #0000b ; or psw, #0001b ; ixe ? 1 add 03h, 11h when the above instruction is executed, the contents of the data memory at address 13h and the contents of the general-purpose register at address 03h are added and the result stored in the general-purpose register at address 03h. this means that the add r, m instruction performs the or operation on the address (in the above case, 11h of bank0) specified by m and the index register value (in the above case, 000000010b), the result becoming the real address (in the above case, 13h of bank0). then, the instruction is executed at the real address. (see fig. 8-5 .) compared to ixe = 0 ( example 1 in section 8.5.3 ), the address of the data memory specified directly by the instruction is modified (or operation) by the index register. example 2. to clear all bank data memories to 0 mov ixl, #0 ; mov ixm, #0 ; ix ? 0 mov ixh, #0 ; loop: or psw, #0001b ; ixe ? 1 mov 00h, #0 ; sets data memory specified by ix to 0. inc ix ; ix ? ix + 1 and psw, #1110b ; ixe ? 0; ixe is not modified by ix because the address ; is 7fh. skt ixm, #0111b ; is row address 7 reached? br loop ; loop if not 7 add ixm, #1 ; specifies the next bank without clearing row address 7. addc ixh, #0 ; skf ixm, #1000b ; were banks cleared up to bank2? skt ixh, #0001b ; br loop ; loop unless cleared
65 m pd17062 fig. 8-5 data memory address modification with ixe = 1 01 2 3 45 6 r 0 1 2 3 4 m add r, m column address row address general- purpose register specified by ix
66 m pd17062 8.6 general-purpose register pointer (rp) the general-purpose register pointer points to the bank and row address of the general-purpose register. however, since rph of the m pd17062 is fixed at 0, only rpl (3 bits) can be specified. this means that 0 to 7 can be specified as a register pointer. hence, in the m pd17062, the row address of the general-purpose register can be specified anywhere within bank0. 8.7 program status word (psword) the program status word consists of a flag that indicates the result of operation by the alu in the cpu and a 5-bit flag that modifies the alu function. psword has a binary coded decimal (bcd) flag, compare (cmp) flag, carry (cy) flag, zero (z) flag, and index enable (ixe) flag. fig. 8-6 shows the functions of these flags. fig. 8-6 configuration of psword b 0 b 3 b 2 b 1 b 0 bcd cmp cy z ixe when the arithmetic operation result is other than 0, this flag is reset. the set condition differs according to the contents of the cmp flag. 7eh 7fh index enable flag when this flag is set, index modification is enabled. zero flag (1) when cmp = 0 the flag is set when the arithmetic operation result is 0. (2) when cmp = 1 the flag is set when the result of the arithmetic operation executed at z = 1 is 0. carry flag the carry flag is set when a carry occurs during the execution of an addition instruction or when a borrow occurs during the execution of a subtraction instruction. this flag is reset when neither carry nor borrow occurs. this flag is set when the least significant bit of the general- purpose register is 1, in which the rorc instruction is executed. the flag is reset when the bit is 0. compare flag when this flag is set, the arithmetic operation result is not stored into data memory. the cmp flag is reset automatically when the skt or skf instruction is executed. bcd flag when this flag is set, all arithmetic operations are executed in decimal. when this flag is not set, all arithmetic operations are executed in binary.
67 m pd17062 9. register file (rf) the register file is a group of registers that mainly control the cpu peripheral circuits. the register file has a capacity of 128 words 4 bits. however, peripheral circuit addresses are actually allocated to the high-order 64 nibbles (00h-3fh) and addresses 40h-7fh of the currently selected bank of data memory to the low-order 64 nibbles (40h-7fh). this means that 40h-7fh of each bank of data memory belongs to both the data memory address space and the register file address space. in the assembler, the control register file is allocated to 80h-bfh.
68 m pd17062 fig. 9-1 configuration of control register (1/2) note the number in parenthesis is the address used when the assembler (as17k) is used. column address row address item 0 1 2 3 4 5 6 7 0 (8) note stack pointer (sp) s p 2 ( s p 1 ( s p 0 ( 000 c e read/ write r/w r 1 (9) note 0 h s c g t 1 0 h s c g t 0 h s c g o s t t 00 0 p l l r f c k 3 p l l r f c k 2 p l l r f c k 1 p l l r f c k 0 0 i n t n c m d 2 i n t n c m d 1 i n t n c m d 0 000 b t m 0 c y read/ write r/w r r/w r/w r 2 (a) note a d c c h 1 a d c c h 0 a d c c m p 000 p l l u l 000 p 1 c g i o read/ write r/w r r/w read/ write r/w r /w r/w r/w r/w r/w 3 (b) note 0 c r o m b n k 00 i d c e n0 0 p l u l s e n 1 p l u l s e n 0 p 1 b b i o 3 p 1 b b i o 2 p 1 b b i o 1 p 1 b b i o 0 p 0 b b i o 3 p 0 b b i o 2 p 0 b b i o 1 p 0 b b i o 0 p 0 a b i o 3 p 0 a b i o 2 p 0 a b i o 1 p 0 a b i o 0 register ce pin level judge register symbol h sync - counter-gate control register h sync - counter-gate judge register register symbol pll refer- ence clock select register int nc mode select register basic timer 0 carry flip-flop judge register register symbol a/d converter control register pll-unlock- flip-flop judge register port 1c group i/o select register idc crom bank register register symbol idc enable register pll-unlock- flip-flop sensibility select register port 1b bit i/o select register port 0b bit i/o select register port 0a bit i/o select register idcdma enable register 0 i d c d m a e n 0 0 0 r/w a d c c h 2 000
69 m pd17062 fig. 9-1 configuration of control register (2/2) 89 a b c d e f s i o 0 c h s b s i o 0 m s s i o 0 t x b t m 0 c k 0 0 i n t v s y n i n t n c r/w r/w 0 i e g v s y n i e g n c b t m 0 z x r s b a c k s i o 0 n w t s i o 0 w r q 1 s i o 0 w r q 0 r/w r/w s i o 0 s f 8 s i o 0 s f 9 s b s t t s b b s y i p n c r r/w 0 s i o 0 i m d 0 0 s i o 0 i m d 1 00 s i o 0 c k 1 s i o 0 c k 0 i r q s i o 0 i r q n c r/w r/w r serial i/o0 mode select register timer 0 clock select register interrupt- level judge register serial i/o0 wait control register interrupt edge selection register serial i/o0 status judge register interrupt enable register serial i/o0 interrupt mode register serial i/o0 clock select register interrupt request register b t m 0 c k 1 b t m 0 c k 2 0 0 i p v s y n i p b t m 0 i r q b t m 0 i r q v s y n i p s i o 0
70 m pd17062 table 9-1 peripheral hardware control functions of control registers (1/5) remark *: retains the previous state. peripheral hardware control register peripheral hardware control function at reset stack timer interrupt register ad- dress read/ write b3 b2 b1 b0 symbol function outline set value 01 777 stack pointer (sp) 01h r/w 0 (sp2) (sp1) (sp0) fixed at 0 stack pointer (3 bits are valid.) btm0zx on/off of zerocross circuit btm0ck2 btm0ck0 0 0 0 btm0cy 0 intvsyn 0 intnc 0 intncmd2 intncmd1 intncmd0 09h r/w 17h r 0fh r 15h r/w timer 0 clock select register btm0ck1 basic timer 0 carry flip-flop judge register interrupt-level judge register int nc mode select register base clock setting of basic timer 0 (internal/external) fixed at 0 detects the carry flip-flop state fixed at 0 detects the v sync pin state fixed at 0 detects the int nc pin state fixed at 0 selects the pulse width of interrupt accept pulse width of the int nc pin no operation operation pulse for timer carry flop-flop set 0: 10 hz (100 ms, internal) 1: 200 hz (5 ms, internal) 2: 10 hz (100 ms, internal) 3: 200 hz (5 ms, internal) 4: f tmin /5 hz (external) 5: 200 hz (5 ms, internal) 6: f tmin /6 hz (external) 7: 200 hz (5 ms, internal) pulse for timer interrupt 0: 200 hz (5 ms, internal) 1: 10 hz (100 ms, internal) 2: 50 hz (20 ms, internal) 3: 50 hz (20 ms, internal) 4: 200 hz (5 ms, internal) 5: f tmin /5 hz (external) 6: 200 hz (5 ms, internal) 7: f tmin /6 hz (external) 00* 011 000 000 reset set low level high level low level high level 0: accepts with edge 1: 200 s 2: 400 s 3: 2 ms 4: 4 ms mm p o w e r o n s t o p c e
71 m pd17062 table 9-1 peripheral hardware control functions of control registers (2/5) remark *: retains the previous state. peripheral hardware control register peripheral hardware control function at reset register ad- dress read/ write b3 b2 b1 b0 symbol function outline set value 01 p o w e r o n s t o p c e interrupt pin pll frequency synthesizer interrupt edge select register interrupt permission register interrupt request register ce pin level judge register pll reference clock select register pll unlock flip-flop judge register pll unlock flip-flop sensibility select register 1fh r/w 2fh r/w 3fh r 07h r 13h r/w 22h r 32h r/w 0 iegvsyn 0 iegnc ipvsyn ipsio0 ipbtm0 ipnc irqvsyn irqsio0 irqbtm0 irqnc 0 0 0 ce pllrfck3 pllrfck2 pllrfck1 pllrfck0 0 0 0 pllul 0 0 plulsen1 plulsen0 fixed at 0 sets the interrupt issue edge (v sync ) fixed at 0 sets the interrupt issue edge (int nc ) - serial interface 0 - v sync signal - basic timer 0 - int nc pin - serial interface 0 - v sync signal - basic timer 0 - int nc pin sets the in- terrupt permis- sion of: sets the in- terrupt request of: fixed at 0 detects the ce pin state fixed at 1 fixed at 0 detects the unlock flip-flop state fixed at 0 sets the set delay time for the unlock flip-flop rising edge falling edge rising edge falling edge 00 0 01 1 interrupt disabled interrupt enabled no interrupt request/ processing in progress interrupt request made 00 0 low level high level 0 2: 6.25 khz 3: 12.5 khz 6: 25 khz f: operation stopped (disabled state) 0, 1, 4, 5, 7-e: setting disabled locked state unlocked state 00 11 01 01 1.25 3.5 0.25 1.5 s 3.75 s 0.5 s mmm disabled state to to to ff * 0* * 00 *
72 m pd17062 table 9-1 peripheral hardware control functions of control registers (3/5) remark *: retains the previous state. **: indefinite peripheral hardware control register peripheral hardware control function at reset register ad- dress read/ write b3 b2 b1 b0 symbol function outline set value 01 p o w e r o n s t o p c e a/d converter general-purpose port serial interface a/d converter controll register port 1c group i/o select register port 1b bit i/o select register port 0b bit i/o select register port 0a bit i/o select register serial i/o0 mode select register serial i/o0 wait control register 21h r/w 27h r/w 35h r/w 36h r/w 37h r/w 08h r/w 18h r/w adcch2 adcch1 adcch0 adccmp 0 0 0 p1cgio p1bbio3 p1bbio2 p1bbio1 p1bbio0 p0bbio3 p0bbio2 p0bbio1 p0bbio0 p0abio3 p0abio2 p0abio1 p0abio0 sio0ch sb sio0ms sio0tx sback sio0nwt sio0wrq1 sio0wrq0 selects the pin used as an a/d converter detects the comparison result fixed at 0 sets i/o of port 1c (group i/o) p1b 3 pin p1b 2 pin p1b 1 pin p1b 0 pin p0b 3 pin p0b 2 pin p0b 1 pin p0b 0 pin p0a 3 pin p0a 2 pin p0a 1 pin p0a 0 pin i/o setting (bit i/o) sets the number of communication lines sets the communication method sets master/slave sets the transfer direction sets and detects acknowledge (i 2 c bus method) sets the wait permission sets the wait mode 0: ad0 2: ad2 4: ad4 6, 7: not to be set 1: ad1 3: ad3 5: ad5 v in < v ref v in > v ref input output input output 2-wire method 3-wire method serial i/o method i 2 c bus method (only for 2-wire method) master operation slave operation reception transmission permitted released sets and detects 0 and 1 011 0 001 1 no wait data wait acknow- ledge wait ad- dress wait 000 000 000 000 000 ** * *
73 m pd17062 table 9-1 peripheral hardware control functions of control registers (4/5) remark *: retains the previous state. **: indefinite peripheral hardware control register peripheral hardware control function at reset register ad- dress read/ write b3 b2 b1 b0 symbol function outline set value 01 p o w e r o n s t o p c e serial interface horizontal synchronizing signal counter serial i/o0 status judge register serial i/o0 interrupt mode register serial i/o0 clock select register h sync counter gate control register h sync counter gate judge register 28h r 38h r/w 39h r/w 11h r/w 12h r sio0sf8 sio0sf9 sbstt sbbsy 0 0 sio0imd1 sio0imd0 0 0 sio0ck1 sio0ck0 0 0 hscgt1 hscgt0 hscgostt 0 0 0 detects the contents of clock counter detects the number of clocks (i 2 c bus method) detects the start condition (i 2 c bus method) fixed at 0 sets the interrupt condition of serial interface 0 fixed at 0 fixed at 0 sets the internal clock of serial interface 0 controls the h sync counter gate detects open/close of the h sync counter fixed at 0 000 resets when the contents of the clock counter become 0 or 1 resets when the contents of the clock counter become 0 or 1 resets when the contents of the clock counter become 8 resets when the contents of the clock counter become 9 sets up the start condition - 9th clock sets up the start condition - stop condition 00 1 1 01 1 0 7th clock 8th clock 7th clock after occur- rence of start condition stop con- dition 00 1 1 01 1 0 gate close gate open 1.69 ms gate open not to be set gate open gate close 00 1 1 01 1 0 100 khz 200 khz 500 khz 1 mhz ** * * ** * * 000 0
74 m pd17062 table 9-1 peripheral hardware control functions of control registers (5/5) peripheral hardware control register peripheral hardware control function at reset register ad- dress read/ write b3 b2 b1 b0 symbol function outline set value 01 p o w e r o n s t o p c e idc idc dma enable register idc crom bank register idc enable register 00h r/w 30h r/w 31h r/w 0 0 0 0 0 0 0 0 0 idcdmaen crombnk idcen fixed at 0 sets the dma mode permission fixed at 0 fixed at 0 fixed at 0 turns the idc display on/off selects the crom bank not permitted permitted bank0 (0800h-0bffh) bank1 (0c00h-0f7fh) display on display off 000 000 000
75 m pd17062 b 3 b 2 b 1 b 0 0 idcdmaen 00 00h 0 1 dma prohibited mode (instruction cycle = 2 s) dma mode (instruction cycle = 12 s) m m 9.1 idcdmaen (00h, b 1 ) this flag must be set to enable the operation of idc. when the idcdmaen flag is set, the mode changes to dma mode and idc is enabled. in dma mode, the instruction cycle is seen as 12 m s. for details, see chapter 20 . 9.2 sp (01h) sp is a pointer that addresses the stack register. b 3 b 2 b 1 b 0 0 (spb 2 ) (spb 0 ) 01h 0 0 0 0 0 1 010 011 100 101 110 111 (spb 1 ) level 6 level 5 level 4 level 3 level 2 level 1 at reset not to be set sp (stack pointer)
76 m pd17062 9.3 ce (07h, b 0 ) ce is a flag for reading the ce pin level. the flag indicates 1 when a high level signal is input to the ce pin, or 0 when a low level signal is input. 9.4 serial interface mode register (08h) b 3 b 2 b 1 b 0 00 ce 07h 0 1 0 ce pin low level ce pin high level b 3 b 2 b 1 b 0 sio0ch sb sio0tx 08h 0 1 sio0ms 0 1 0 1 0 1 transmission/reception setting setting of serial interface clock direction setting of serial interface mode setting of serial interface channel 2-wire bus mode ch0 serial i/o mode ch1 serial i/o mode : rx (reception) mode : si mode : p0a 3 used as a general-purpose port 2-wire bus mode ch0 serial i/o mode ch1 serial i/o mode : tx (transmission) mode : so mode : p0a 3 used as an so pin 2-wire bus mode serial i/o mode : slave operation : external clock operation 2-wire bus mode serial i/o mode : master operation : internal clock operation serial i/o mode 2-wire bus mode selects ch0 selects ch1
77 m pd17062 b 3 b 2 b 1 b 0 btm0zx btm0ck2 btm0ck0 09h btm0ck1 0 1 0 0 0 0 0 1 010 011 100 101 110 111 timer int timer carry 5 ms 100 ms 20 ms 20 ms 5 ms 5/f tmr s 5 ms 6/f tmr s 100 ms 5 ms 100 ms 5 ms 5/f tmr s 5 ms 6/f tmr s 5 ms time base setting internal internal internal internal internal external internal external internal internal internal internal external internal external internal zerocross setting zerocross off zerocross on 9.5 btm0md (09h) 9.6 intvsyn (0fh, b 2 ) the intvsyn flag is used for reading the vertical synchronous signal level. when a high level signal is input to the v sync pin, the flag is set to 1. when a low level signal is input to the v sync pin , the flag is reset to 0.
78 m pd17062 9.7 intnc (0fh, b 0 ) the int nc flag is used for reading the int nc pin state. the flag indicates 1 when a high level signal is input to the int nc pin, and 0 when a low level signal is input to the int nc pin. 9.8 horizontal synchronizing signal counter control (11h, 12h) b 3 b 2 b 1 b 0 0 intvsyn intnc 0fh 0 0 1 0 1 the v sync pin is low level. the v sync pin is in the high level period. the int nc pin is low level. the int nc pin is high level. b 3 b 1 b 0 hscgostt 0 12h 0 0 1 b 3 b 2 b 1 b 0 hscgt3 hscgt2 hscgt0 11h hscgt1 0 0 1 1 0 1 0 1 0 b 2 input confirmation of gate open/close of horizontal synchronizing signal counter both bits are fixed at 0. gate close gate open gate open (1.69 ms interval) not to be set gate close gate open setting of horizontal synchronizing signal counter
79 m pd17062 9.9 pll reference mode selection register (13h) 9.10 setting of int nc pin acceptance pulse width (15h) b 3 b 2 b 1 b 0 pllrfck3 pllrfck2 pllrfck0 13h pllrfck1 0010 0011 0110 1111 0111 1010 1011 1110 6.25 khz 12.5 khz 25 khz pll disabled not to be set reference frequency f r setting fixed at 1 b 3 b 2 b 1 b 0 intncmd3 intncmd2 intncmd0 15h intncmd1 000 001 010 011 100 edge (no noise canceler) 200 s 2 ms setting of int nc pin acceptance pulse width fixed at 0 4 ms 400 s m m
80 m pd17062 9.11 timer carry (17h) 9.12 serial interface wait control (18h) 9.13 iegnc (1fh) the iegnc flag is used for selecting the interrupt detection edge of the int nc pin and v sync pin. when the flag is set to 0, an interrupt occurs at a rising edge. when the flag is set to 1, an interrupt occurs at a falling edge. b 3 b 2 b 1 b 0 17h exclusive flag for reading timer carry 000 btm0cy this flag is set according to the selected time base, and reset when the timer carry is read. b 3 b 2 b 1 b 0 18h setting of wait timing 0 1 sback sio0nwt sio0wrq1 sio0wrq0 00 01 10 11 2-wire bus mode serial i/o mode does not wait does not wait waits when the clock falls with the contents of the clock counter being 8 waits when the clock falls with the contents of the clock counter being 9 waits when the clock falls with the contents of the clock counter being 8 after detection of the start condition waits when the contents of the clock counter become 9 waits when the contents of the clock counter become 9 not to be set wait setting acknowledgement at 2-wire bus mode forced wait wait released b 3 b 2 b 1 b 0 0 iegvsyn iegnc 1fh 0 0 1 0 1 interrupt occurs at the rising edge of the v sync pin interrupt occurs at the falling edge of the v sync pin interrupt occurs at the rising edge of the int nc pin interrupt occurs at the falling edge of the int nc pin
81 m pd17062 b 3 b 2 b 1 b 0 adcch2 adcch1 adccmp 21h adcch0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 0 0 1 1 0 1 0 1 adc 0 select adc 1 select, shared with p1c 3 adc 2 select, shared with p0d 0 adc 3 select, shared with p1d 1 adc 4 select, shared with p0d 2 adc 5 select, shared with p0d 3 no corresponding channel (not to be set) a/d converter input channel select 9.14 a/d convertor control (21h) 9.15 pll unlock flip-flop judge register (22h) b 3 b 2 b 1 b 0 0 0 pllul 22h 0 1 0 detects the unlock flip-flop state unlock flip-flop = 0: pll locked unlock flip-flop = 1: pll unlocked
82 m pd17062 9.16 port1c i/o setting (27h) 9.17 serial i/o0 status register (28h) b 3 b 2 b 1 b 0 sio0sf8 sio0sf9 sbbsy 28h 0 1 sbstt busy condition detection 0 1 start condition detection 0 1 9 clock detection 0 1 8 clock detection detects the stop condition detects the start condition resets when the contents of the clock counter become 9 detects the start condition resets when the contents of the clock counter become 0 or 1 sets when the contents of the clock counter become 9 resets when the contents of the clock counter become 0 or 1 sets when the contents of the clock counter become 8 b 3 b 2 b 1 b 0 0 0 p1cgio 27h 0 1 0 p1c port i/o setting p1c 1 , p1c 2 , p1c 3 : input port p1c 1 , p1c 2 , p1c 3 : output port
83 m pd17062 9.18 interrupt permission flag (2fh) this flag is used to enable interrupt for each interrupt cause. when the flag is set to 1, interrupt is enabled. when the flag is set to 0, interrupt is disabled. 9.19 crom bank selection (30h) b 3 b 2 b 1 b 0 ipsio0 ipvsyn ipnc 2fh 0 1 ipbtm0 0 1 0 1 0 1 interrupt from the int nc pin disabled interrupt from the int nc pin enabled interrupt from the clock timer disabled interrupt from the clock timer enabled interrupt from the v sync pin disabled interrupt from the v sync pin enabled interrupt from the serial interface disabled interrupt from the serial interface enabled b 3 b 2 b 1 b 0 0 0 crombnk 30h 0 1 0 crom address setting crom address 0800h-0bffh crom address 0c00h-0f7fh
84 m pd17062 9.20 idcen (31h) 9.21 pll unlock flip-flop delay control register (32h) b 3 b 2 b 1 b 0 0 0 idcen 31h 0 1 0 idc operation prohibited (display off) idc operation start (display on) b 3 b 2 b 1 b 0 plulsen3 32h 0 0 1 1 0 1 0 1 plulsen2 plulsen1 plulsen0 1.25 to 1.5 s or more 3.5 to 3.75 s or more 0.25 to 0.5 s or more unlock flip-flop disable (always set) fixed at 0 setting of the delay time of the reference frequency f r and divided frequency f n required for setting the unlock flip-flop m m m
85 m pd17062 9.22 p1bbion (35h) p1bbion specifies the port1b i/o. when p1bbion is set to 0, port1b becomes an input port. when p1bbion is set to 1, port1b becomes an output port. 9.23 p0bbion (36h) p0bbion specifies the port0b i/o. when p0bbion is set to 0, port0b becomes an input port. when p0bbion is set to 1, port0b becomes an output port. b 3 b 2 b 1 b 0 p0bbio3 p0bbio2 p0bbio0 36h 0 1 p0bbio1 p0b 0 i/o setting 0 1 p0b 1 i/o setting 0 1 p0b 2 i/o setting 0 1 p0b 3 i/o setting p0b 0 input port p0b 0 output port p0b 1 input port p0b 1 output port p0b 2 input port p0b 2 output port p0b 3 input port p0b 3 output port b 3 b 2 b 1 b 0 p1bbio3 p1bbio2 p1bbio0 35h 0 1 p1bbio1 p1b 0 i/o setting 0 1 p1b 1 i/o setting 0 1 p1b 2 i/o setting 0 1 p1b 3 i/o setting p1b 0 input port p1b 0 output port p1b 1 input port p1b 1 output port p1b 2 input port p1b 2 output port p1b 3 input port p1b 3 output port
86 m pd17062 9.24 p0abion (37h) p0abion specifies the port0a i/o. when p0abion is set to 0, port0a becomes an input port. when p0abion is set to 1, port0a becomes an output port. 9.25 setting of interrupt request generation timing in serial interface mode (38h) b 3 b 2 b 1 b 0 p0abio3 p0abio2 p0abio0 37h 0 1 p0abio1 p0a 0 i/o setting 0 1 p0a 1 i/o setting 0 1 p0a 2 i/o setting 0 1 p0a 3 i/o setting p0a 0 input port p0a 0 output port p0a 1 input port p0a 1 output port p0a 2 input port p0a 2 output port p0a 3 input port p0a 3 output port b 3 b 2 b 1 b 0 sio0imd3 sio0imd2 sio0imd0 38h sio0imd1 00 01 10 11 function fixed at 0 interrupt request generated at rising edge of the 7th bit of the shift clock interrupt request generated at rising edge of the 8th bit of the shift clock interrupt request generated when the stop condition is detected interrupt request generated at rising edge of the 7th bit of the shift clock immediately after the start condition is detected
87 m pd17062 9.26 shift clock frequency setting (39h) 9.27 irqnc (3fh) irqnc is an interrupt request flag that indicates the interrupt request state. when an interrupt request is generated, the flag is set to 1. when the request is accepted (interrupt is made), the flag is reset to 0. the interrupt request flag can be read and written by the program. hence, if 1 is written, an interrupt by software can be generated. if 0 is written, the interrupt hold status can be released. the irqnc flag becomes 0 upon reset. b 3 b 2 b 1 b 0 sio0ck3 sio0ck2 sio0ck0 39h sio0ck1 00 01 10 11 100 khz 200 khz 500 khz 1 mhz fixed at 0 internal clock frequency flag name bit position interrupt source irqnc b 0 int nc pin irqbtm0 b 1 clock timer irqvsyn b 2 v sync pin irqsio0 b 3 serial interface
88 m pd17062 10. data buffer (dbf) the data buffer is used to transfer data to and from peripheral hardware and to reference tables. 10.1 data buffer structure 10.1.1 mapping of data buffer to data memory fig. 10-1 shows how the data buffer is mapped to data memory. as shown in fig. 10-1, the data buffer is allocated to addresses 0ch to 0fh of data memory bank0 and consists of 16 bits in a 4-word 4-bit configuration. because the data buffer is mapped to data memory, it can be operated by data memory instructions. fig. 10-1 data buffer map 0123456789abcdef data buffer data memory bank0 bank1 bank2 system register 7 7 0 1 2 3 4 5 6 7 column address low address
89 m pd17062 10.1.2 data buffer structure fig. 10-2 shows the data buffer structure. as shown in fig. 10-2, the data buffer consists of 16 bits. bit b 0 of data memory address 0fh is the lsb, and bit b 3 of data memory address 0ch bit 3 is the msb. fig. 10-2 data buffer structure b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0ch 0dh 0eh 0fh dbf3 dbf2 dbf1 dbf0 m s b l s b data memory address bit bit symbol data data buffer data
90 m pd17062 10.2 functions of data buffer the data buffer provides the following two functions: (1) read constant data in program memory (to reference tables) (2) transfer data to and from peripheral hardware fig. 10-3 shows the relationship between the data buffer, peripheral hardware, and memory. table referencing is described in section 10.3 , and the peripheral hardware is described in sections 10.4 to 10.6 . fig. 10-3 relationship between data buffer, peripheral hardware, and memory 01h 02h 03h 04h 05h-08h 40h 41h peripheral address data buffer internal table referencing peripheral hardware image display controller (idc) a/d converter serial interface horizontal synchronizing signal counter 6-bit d/a converter address register (ar) pll frequency synthesizer program memory (rom) constant data
91 m pd17062 10.3 data buffer and table referencing 10.3.1 table referencing tables are referenced by reading the constant data from program memory into the data buffer. this is done using the movt dbf, @ar instruction. therefore, if display data or other constant data is written to program memory in advance and a table reference instruction is executed, writing of a complex data conversion program is unnecessary. the movt instruction is described below. a example program is given in section 10.3.2 . movt dbf, @ar ; reads the contents of the program memory addressed by the address register into the data buffer as shown below. when a table reference instruction is executed, the stack is used one level. because the address register (ar) has only eight valid bits, program memory available for table reference is limited to 256 steps from address 0000h to address 00ffh. see also chapter 4 and section 8.1 . 16 movt dbf, @ ar dbf3 dbf2 dbf1 dbf0 b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 constant data data buffer program memory (rom) specifies the program memory address
92 m pd17062 10.3.2 example table referencing program this section shows an example table referencing program. example p0a mem 0.70h ; p0b mem 0.71h ; p0c mem 0.72h ; org 0000h start : br main data : dw 0001h ; constant data dw 0002h ; dw 0004h ; dw 0008h ; dw 0010h ; dw 0020h ; dw 0040h ; dw 0080h ; dw 0100h ; dw 0200h ; dw 0400h ; dw 0800h ; main : bank0 ; built-in macro set4 p0abio3, p0abio2, p0abio1, p0abio0 set4 p0bbio3, p0bbio2, p0bbio1, p0bbio0 mov rpl, #1110b ; sets general-purpose register to row address 7h of bank0 . mov ar1, #(.dl.data shr 4 and 0fh) mov ar0, #(.dl.data shr 0 and 0fh) ; sets address register to 0001h. loop : ; # movt dbf, @ar ; transfers the contents of the rom specified by ar to data ; buffer. ; $ ld p0a, dbf2 ; transfers the contents of data buffer to port0a (70h), ld p0b, dbf1 ; port0b(71h), and port0c (72h) port data registers. ld p0c, dbf0 add ar0, #1 ; increments the contents of data register by one. addc ar1, #0 skne ar0, #0ch ; writes 0 in ar0 when the value of ar0 reaches 0ch. mov ar0, #0 ; br loop
93 m pd17062 this program sequentially reads the constant data stored at program memory addresses 0001h to 000ch into the data buffer ( # ) and outputs the data to port0a, port0b, and port0c ( $ ). the constant data is left-shifted one bit. as a result, a high-level data is sequentially output to the port0a, port0b, and port0c pins. 10.4 data buffer and peripheral hardware 10.4.1 how to control peripheral hardware the following peripheral hardware units transfer data via the data buffer: ? image display controller ? a/d converter ? serial interface ? horizontal synchronizing signal counter ? 6-bit d/a converter ? address register ? pll frequency synthesizer the peripheral hardware is controlled by setting the data in the peripheral hardware via the data buffer or reading its data. each peripheral hardware unit is provided with a data transfer register called a peripheral register. an address, called a peripheral address, is allocated to each peripheral hardware unit. data transfer between the data buffer and peripheral hardware can be performed by executing a get or put instruction (dedicated to the peripheral register) for the peripheral register. the get and put instructions are described below. the peripheral hardware and data buffer functions are listed in table 10-1. get dbf, p; reads the data of the peripheral register at address p into the data buffer. put p, dbf; writes the data of the data buffer to the peripheral register at address p. there are three types of peripheral registers: write/read (put/get), write only (put), and read only (get). device operation when a get or put instruction is executed for a write only (put only) or read only (get only) peripheral register is described below. ? when a read (get) instruction is executed for a write only (put only) peripheral register, an undefined value is returned. ? when a write (put) instruction is executed for a read only (get only), it has no effect. be careful when using a 17k series assembler and emulator. for details, see section 10.6 .
94 m pd17062 table 10-1 peripheral hardware and data buffer functions data buffer and data transfer function peripheral register peripheral hardware name symbol peri- put data valid explanation pheral instruction/ buffer bits address get i/o bits instruction image display idc start posi- idcorg 01h put/get 8 7 sets the image display controller tion setting controller display start register position. a/d converter a/d converter adcr 02h put/get 8 4 sets the ad converter v ref data comparison voltage register v ref . v ref = x C 0.5 v dd (v) 16 1 x 15 serial interface presettable sio0sfr 03h put/get 8 8 sets the serial out data shift register and reads the serial in data. horizontal syn- hsync hsc 04h get 8 6 reads the value of the chronizing signal counter data horizontal synchroni- counter register zing signal counter. pwm 0 pwm data pwmr0 05h put/get 8 7 sets the d/a converter pin register 0 output signal duty. pwm 1 pwm data pwmr1 06h duty d = x + 0.75 (%) pin register 1 64 pwm 2 pwm data pwmr2 07h 0 x 63 pin register 2 frequency f = 15.625 khz pwm 3 pwm data pwmr2 08h pin register 3 address register address ar 40h put/get 16 16 reads of writes data register from or to the address register. pll frequency pll data pllr 41h put/get 16 16 sets the pll frequency synthesizer register synthesizer frequency division ratio. 6-bit d/a conver- ter (pwm output)
95 m pd17062 10.4.2 precautions when transferring data with peripheral registers data is transferred between the data buffer and peripheral registers in 8-bit or 16-bit units. a put or get instruction is executed for one instruction cycle (2 m s) even if the data is 16 bits long. when 8-bit data transfer is performed but the peripheral register execution data is seven bits, for example, long one extra bit is added. at data write, the status of this extra data is dont care as shown in example 1. at data read, the status of this extra data is unpredictable as shown in example 2. example 1. put instruction (when the valid peripheral register bits are seven bits from bit 0 to bit 6 .) when 8-bit data is written to a peripheral register, the status of the eight high-order bits of the data buffer (contents of dbf3 and dbf2) is dont care. of the 8-bit data in the data buffer, the status of each bit that does not correspond to a valid bit in the peripheral register is dont care. dbf3 dbf2 dbf1 dbf0 b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 peripheral register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 put data buffer 8 0 or unpredictable don't care don't care don't care (can be any value) valid bits
96 m pd17062 example 2. get instruction when the 8-bit data of a peripheral register is read, the value of the eight high-order bits (dbf3 and dbf2) of the data register does not change. of the 8-bit data of the data register, each bit that is not a valid peripheral register bit becomes 0 or unpredictable. whether the bit becomes 0 or unpredictable is decided in advance for each peripheral register. 10.4.3 state at peripheral register reset the valid bits of each peripheral register are reset as follows: dbf3 dbf2 dbf1 dbf0 b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 peripheral register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 get data buffer 8 don't care don't care 0 or unpredictable 0 or unpredictable the value of the peripheral register is read without alteration. valid bits reset valid bit state power-on unpredictable clock-stop previous state held ce previous state held
97 m pd17062 10.5 data buffer and peripheral registers sections 10.5.1 to 10.5.7 describe the data buffer and the peripheral registers. 10.5.1 idc start position setting register fig. 10-4 shows the functions of the idc start position setting register. the idc start position setting register sets the idc display start position. fig. 10-4 idc start position register functions dbf3 0ch dbf2 0dh dbf1 0eh dbf0 0fh b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 d7 d6 d5 d4 d3 d2 d1 d0 idcorg 01h symbol peripheral address peripheral hardware idc display position setting name peripheral register name data buffer symbol address bit data don't care don't care transfer data get put idc start position setting register valid data image display controller d7 to d4: horizontal start position d3 to d0: vertical start position
98 m pd17062 10.5.2 a/d converter data register fig. 10-5 shows the functions of the a/d converter data register. the a/d converter data register sets the a/d converter comparison voltage. because the a/d converter is a 4-bit converter, the four low-order bits of the a/d converter data register are valid. fig. 10-5 a/d converter data register functions dbf3 0ch dbf2 0dh dbf1 0eh dbf0 0fh b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 adcr 02h a/d converter comparison voltage v ref setting 0000 1 x 15 8 v ref = 0 v fixed at 0 v ref =v dd (v) x - 0.5 15 a/d converter symbol peripheral address peripheral hardware name peripheral register name data buffer symbol address bit data don't care don't care transfer data get put a/d converter data register valid data
99 m pd17062 10.5.3 presettable shift register fig. 10.6 shows the functions of the presettable shift register. the presettable shift register writes the serial interface serial out data and reads the serial interface serial in data. fig. 10-6 relationship between presettable shift register and data buffer serial interface serial data is output while being shifted sequentially the data from the msb (bit b 7 ) of the presettable shift register. during serial data input, data is shifted sequentially from the lsb (bit b 0 ). dbf3 0ch dbf2 0dh dbf1 0eh dbf0 0fh b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 d7 d6 d5 d4 d3 d2 d1 d0 sio0sfr 03h serial out data write and serial in data read 12345678 msb lsb data output timing d7 d6 d5 d4 d3 d2 d1 d0 12345678 msb lsb data input timing d7 d6 d5 d4 d3 d2 d1 d0 8 symbol peripheral address peripheral hardware name peripheral register name data buffer symbol address bit data don't care don't care transfer data get put valid data presettable shift register serial interface serial out data clock serial in data clock
100 m pd17062 10.5.4 hsync counter data register fig. 10.7 shows how the hsync counter data register functions . the hsync counter data register reads the horizontal synchronizing signal count. when the hsync counter data register reaches 3fh, it returns to 00h at the next input. fig. 10-7 hsync data register functions dbf3 0ch dbf2 0dh dbf1 0eh dbf0 0fh b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 hsc 04h 00 8 horizontal synchronizing signal count symbol peripheral address peripheral hardware name peripheral register name data buffer symbol address bit data don't care don't care transfer data get hsync counter data register horizontal synchronizing signal counter valid data
101 m pd17062 10.5.5 pwm data register fig. 10-8 shows how the pwm data register functions. the pwm data register sets the duty cycle of the 6-bit d/a converter (pwm output) output. the 6-bit d/a converter has four channels (pins pwm 3 , pwm 2 , pwm 1 , and pwm 0 ). because the duty cycle can be set independently for each channel, four independent pwm duty cycle registers are also provided. fig. 10-8 pwm data register functions dbf3 0ch dbf2 0dh dbf1 0eh dbf0 0fh b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 pwmr0 05h set the pwm output duty of each pin. 0 x 63 8 use pwm pins as d/a converter. duty d = x + 0.75 64 pwm 0 pin pwm0 data register pwmr1 06h 0 pwm 1 pin pwm1 data register pwmr2 07h 0 pwm 2 pin pwm2 data register pwmr3 08h 0 pwm 3 pin pwm3 data register (%) 0 0 use pwm as 1-bit output pin. output contents of b 5 . symbol peripheral address peripheral hardware name peripheral register name data buffer symbol address bit data don't care don't care transfer data get put valid data frequency f = 15.625 khz (f: pwm output repetition frequency)
102 m pd17062 10.5.6 address registers the address registers are mapped to addresses 74h to 77h in the system register (at data memory addresses 74h to 7fh). they are used for program memory address operations. see chapter 8 . the address registers can be used to manipulate data directly with data memory operation instructions. they can also be used to transfer data via the data buffer as part of the peripheral hardware. in other words, data can be read and written via the data buffer with put and get instructions, as well as data memory operation instructions. fig. 10-9 shows the relationship between the address registers and the data buffer. fig. 10-9 relationship between address registers and data buffer dbf3 0ch dbf2 0dh dbf1 0eh dbf0 0fh b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 ar 40h address register data write and read 0000 f 16 address register b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 0000 0 x f 0 0 0 0 ar3 ar2 ar1 ar0 74h 75h 76h 77h name symbol address data address register x symbol peripheral address peripheral hardware peripheral register name data buffer symbol address bit data transfer data get put valid data name address register the eight high-order bits of the address registers are always 0.
103 m pd17062 10.5.7 pll data register fig. 10-10 shows how the pll data register functions. the pll data register sets the frequency division ratio of the pll frequency synthesizer. for the pulse swallow method, all 16 bits are valid, the 12 high-order bits are set in the program counter, and the remaining four low-order bits are set in the swallow counter. fig. 10-10 pll data register dbf3 0ch dbf2 0dh dbf1 0eh dbf0 0fh b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 pllr 41h pll frequency synthesizer frequency division ratio 16 b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 256 (0100h) x 0 (0000h) 2 16 - 1 (0ffffh) not to be set. frequency division ratio n:n = x pll frequency synthesizer symbol peripheral address peripheral hardware name data buffer symbol address bit data transfer data get put name pllr data register peripheral register valid data
104 m pd17062 10.6 precautions when using data buffers 10.6.1 write only, read only, and unused address data buffer precautions when the 17k series assembler and emulator are used for data transfer with peripheral hardware via the data buffer, note the following regarding unused peripheral addresses and write only (put only) and read only (get only) peripheral registers. (1) device operation reading from a write only peripheral register returns an unpredictable value. writing to a read only register does not change its contents. reading from an unused address returns an unpredictable value. writing to an unused address does not change its contents. (2) when using an assembler an instruction that reads from a write only register generates an error. an instruction that writes to a read only register generates an error. an instruction that reads from or writes to an unused address generates an error. (3) when using an emulator (used to execute instructions by batch processing, etc.) reading from a write only register returns an unpredictable value and does not generate an error. writing to a read only register does not change its contents and does not generate an error. reading from an unused address returns an unpredictable value. writing to an unused address does not change its contents and does not generate an error.
105 m pd17062 10.6.2 peripheral register addresses and reserved words when a 17k series assembler is used, no error is generated when peripheral address p is specified directly (with a numerical value) in put p, dbf or get dbf, p as shown in example 1. however, to reduce program bugs, this method should be avoided. therefore, the peripheral addresses should be symbolically defined with symbol definition instructions (an assembler pseudo instructions), as shown in example 2. to simplify symbol definition, peripheral addresses are predefined in the assembler as reserved words. therefore, if reserved words are used, a program can be written without performing symbol definition, as shown in example 3. the reserved words of peripheral registers are shown in the symbol field in table 10-1 and the symbol field in figs. 10-4 to 10-10. example 1. put 02h, dbf ; the assembler does not generate an error if peripheral get dbf, 03h ; addresses are directly specified by 02h and 03h. how ; ever, to reduce program bugs, this method should be ; avoided. 2. sio0data dat 03h ; assigns sio0data to 03h using a symbol definition put sio0data, dbf ; instruction. 3. put sio0sfr ; if reserved word sio0sfr is used, symbol definition is ; unnecessary.
106 m pd17062 11. interrupt an interrupt temporarily stops the program being executed in response to a request from the peripheral hardware (int nc pin, timer, v sync pin or serial interface). the interrupt then branches the program flow to a predetermined address (vector address). 11.1 interrupt block configuration fig. 11-1 shows the interrupt block configuration. the interrupt block consists of the interrupt request control blocks, interrupt enable flip-flop (inte), stack pointer, address stack register, program counter, and interrupt stack. the interrupt request control blocks control interrupt requests from the int nc pin, timer, v sync pin, and serial interface. the interrupt enable flip- flop (inte) sets all interrupt permissions. the stack pointer, address stack register, program counter, and interrupt stack are controlled when an interrupt is accepted. the interrupt request processing block in the peripheral hardware consists of the irq flip-flop, ip flip-flop, and vector address generator (vag). the irq flip-flop detects an interrupt request, the ip flip- flop sets an interrupt permission, and the vector address generator (vag) specifies a vector address at interrupt acceptance. the irq flip-flop and ip flip-flop correspond to the interrupt request flag and interrupt permission flag, respectively, in the control register in one-to-one ratio.
107 m pd17062 fig. 11-1 interrupt block configuration 3fh 2fh b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 i r q s i o 0 i r q v s y n i r q b t m 0 i r q n c i p s i o 0 i r v s y n i p b t m 0 i p n c 01h b 3 b 2 b 1 b 0 0 s p 2 s p 1 s p 0 bank psw b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 79h 7fh 00 c m p c y zi x e system register symbol address bit program counter address stack register asr0 asr1 asr5 control register ipsio0 irqsio0 vag 01h ipvsyn irqvsyn vag 02h ipbtm0 irqbtm0 vag 03h ipnc irqnc vag 04h flag symbol name interrupt request (intreq) interrupt permission (intpm) stack pointer (sp) address bit serial inter- face v sync pin timer int nc pin stack pointer flag symbol interrupt stack interrupt request processing block interrupt enable flip-flop inte di or ei instruction
108 m pd17062 11.2 interrupt function the following peripheral hardware can use the interrupt function: the int nc pin, timer, v sync pin, and serial interface. if the peripheral hardware satisfies the specified condition (e.g., a falling edge is input to the int nc pin), the interrupt function temporarily stops the program being executed and starts the exclusive processing program. the interrupt signal sent from the peripheral hardware at this time is called an interrupt request. outputting an interrupt signal can be expressed as issuing an interrupt signal. the exclusive processing program for interrupts is called the interrupt processing routine. when an interrupt is accepted, processing is branched to the program memory address (vector address) specified for each interrupt source. each interrupt processing routine can be started from this vector address. processing for the interrupt function can be divided into the processing done before interrupt acceptance and the processing done after interrupt acceptance. first, the interrupt function operates until the interrupt request from the peripheral hardware is accepted. then, after the interrupt is accepted, the interrupt function branches processing to the vector address and returns control to the program that was interrupted. sections 11.2.1 to 11.2.8 describe the functions of the blocks shown in fig. 11-1. 11.2.1 peripheral hardware there are four peripheral hardware interrupt functions: the int nc pin, timer, v sync pin, and serial interface. interrupt request issuance conditions can be set for each type of peripheral hardware. for example, the request issuance timing for the int nc pin (rising or falling edge of the signal applied to the int nc pin) can be selected. see sections 11.3 to 11.7 for details of interrupt request issuance conditions for the peripheral hardware. 11.2.2 interrupt request processing block an interrupt request processing block is provided for each type of peripheral hardware. this block controls interrupt request permits an interrupt, and generates the vector address at interrupt acceptance. sections 11.2.3 to 11.2.8 describe the flags of the interrupt request processing block. 11.2.3 interrupt request flags (irq ) the interrupt request flags are set to 1 when an interrupt request is issued from the peripheral hardware. these flags are reset to 0 when the interrupt request is accepted. because the interrupt request flags correspond one-to-one to the flags in the interrupt request register, they can be read and written via the window register. writing a 1 via the window register has the same effect as issuing an interrupt request. once these flags are set, they are not reset until the corresponding interrupts are accepted or a 0 is written via the window register. even if two or more interrupt requests are issued together, the interrupt request flags corresponding to the unaccepted interrupts are not reset. these flags are reset to 0 at power-on reset, clock stop, or ce reset.
109 m pd17062 11.2.4 interrupt permission flags (ip ) the interrupt permission flags set interrupt permissions for various types of peripheral hardware. if these flags are set to 1 and the corresponding interrupt request flags are also set, the corresponding interrupt requests are output. because these flags correspond one-to-one to the flags in the interrupt permission register of the control register, they are read and written via the window register. these flags are reset to 0 at power-on reset, clock stop, or ce reset. 11.2.5 vector address generator (vag) when interrupts from various types of peripheral hardware are accepted, the vector address generator generates the branch address (vector address) of the program memory for the source of the accepted interrupt. table 11-1 lists the vector addresses corresponding to the interrupt sources. table 11-1 interrupt vector addresses interrupt source vector address int nc pin 04h timer 03h v sync pin 02h serial interface 01h
110 m pd17062 11.2.6 interrupt enable flip-flop (inte) the interrupt enable flip-flop sets the interrupt permissions of all four types of interrupts. if each interrupt request processing block outputs a 1 while this flip-flop is set to 1, a 1 is output from this flip-flop and an interrupt is accepted. even if a 1 is output from each interrupt request processing block while this flip-flop is reset to 0, an interrupt is not accepted. to set or reset this flip-flop, use exclusive instructions ei (set) and di (reset). if the ei instruction is executed, this flip-flop is set when the instruction executed after the ei instruction is completed. if the di instruction is executed, the flip-flop is reset during the di instruction execution cycle. if an interrupt is accepted while the interrupt enable flip-flop is set (ei state), this flip-flop is reset (di state). even if the di instruction is executed in the di state or the ei instruction is executed in the ei state, the instruction is invalid. this flag is reset (di state) at power-on reset, clock stop, or ce reset. 11.2.7 stack pointer, address stack register, and program counter the return address of control returned from the interrupt processing routine is saved in the address stack register. the stack pointer specifies one of six address stack registers (asr0 to asr5) to be used. in other words, when an interrupt is accepted, the stack pointer value is reduced by 1, and the program counter value is saved in the address stack register indicated by the stack pointer. next, if exclusive return instruction reti is executed after the interrupt processing routine, the contents of the address stack register indicated by the stack pointer are returned to the program counter. at this time, the stack pointer value is increased by 1. see also chapter 4 . 11.2.8 interrupt stack the interrupt stack saves the contents of the bank register and index enable flag in the system register when an interrupt is accepted. when the interrupt is accepted and the contents of the bank register and index enable flag are saved, the bank register and index enable flag in the system register are reset to 0. the interrupt stack can save the contents of the bank registers and index enable flags of up to two levels. therefore, the interrupt stack can issue multiple interrupts of up to two levels; for example, an interrupt can be accepted during execution of a routine that is processing another interrupt. the contents of the interrupt stack are restored in the bank register and index enable flag in the system register by executing the reti instruction. the reti instruction is exclusively used to return control from the interrupt processing routine. see also chapter 4 .
111 m pd17062 11.3 interrupt acceptance 11.3.1 interrupt acceptance and priority an interrupt is accepted as follows: (1) when the interrupt conditions are satisfied (e.g., a rising edge is input to the int nc pin), each type of peripheral hardware outputs the interrupt request signal to the interrupt request blocks. (2) when an interrupt request block accepts an interrupt request signal from the peripheral hardware, it sets the corresponding irq flag to 1 (e.g., sets irqnc for the int nc pin). (3) if an interrupt permission flag corresponding to an irq (e.g., ipnc flag for the irqnc flag) is set 1 when each interrupt request flag is set, each interrupt request block outputs a 1. (4) a signal output from each interrupt request block is input to the interrupt enable flip-flop via an or circuit. this interrupt enable flip-flop is set to 1 by the ei instruction and reset by the di instruction. if a 1 is output from each interrupt request block while the interrupt enable flip-flop is set, a 1 is output from the interrupt enable flip-flop and the interrupt is accepted. when the interrupt is accepted, the signal from the interrupt enable flip-flop is input to the interrupt request block via an and circuit as shown in fig. 11-1. the interrupt request flag is reset by the signal input to each interrupt request block, and the vector address for each interrupt is output. if a 1 is output from the interrupt request block at this time, the interrupt acceptance signal is not transferred to the next level. if two or more interrupt requests are issued together, they are accepted in the following sequence: (dma) > int nc pin > timer > v sync pin > serial interface this sequence is called the hardware priority. fig. 11-2 shows the interrupt acceptance flowchart. the processing in # of fig. 11-2 is always executed in parallel. if two or more interrupt requests are generated at the same time, the interrupt request flags are set at the same time. on the other hand, the processing in $ is executed according to the priority given by the interrupt permission flags. in other words, if an interrupt permission flag is not set, the interrupt from the interrupt source is not accepted. an interrupt with a high hardware priority can be inhibited by resetting the corresponding interrupt permission flag in the program. this type of interrupt is called a maskable interrupt. for a maskable interrupt, an interrupt with a high hardware priority can be inhibited by the program; therefore, it is also called the software priority.
112 m pd17062 fig. 11-2 interrupt acceptance flowchart start int nc pin timer v sync pin serial interface ipnc=1? ipbtm0=1? ipvsyn=1? ipsio0=1? no yes no yes no yes no yes yes no yes no yes no irqnc= ipnc=1? irqbtm0= ipbtm0=1? irqvsyn= ipvsyn=1? irqsio0= ipsio0=1 # $ no yes interrupt request? no yes interrupt request? no yes interrupt request? no yes interrupt request? no yes irqnc setting irqbtm0 setting irqvsyn setting irqsio0 setting ei state? interrupt acceptance irqnc resetting irqbtm0 resetting irqvsyn resetting irqsio0 resetting
113 m pd17062 11.3.2 timing chart at interrupt acceptance fig. 11-3 shows the timing chart at interrupt acceptance. fig. 11-3 (1) shows the timing chart of one interrupt. the timing chart when an interrupt request flag is set to 1 is shown in (a) of (1). the timing chart when an interrupt permission flag is set to 1 is shown in (b) of (1). in both cases, the interrupt is accepted when the interrupt request flag, interrupt enable flip-flop, and interrupt permission flag are all set. if the flag or flip-flop that is set satisfies the skip conditions or the conditions for the first instruction cycle of the movt dbf or @ar instruction, the interrupt is accepted after execution of the skipped instruction (becomes nop) or the second instruction cycle of the movt dbf or @ar instruction. the interrupt enable flip-flop is set in the instruction cycle after the cycle in which the ei instruction is executed. fig. 11-3 (2) shows the timing chart when two or more interrupts are used. if all interrupt permission flags are set when two or more interrupts are used, the interrupt with the highest hardware priority is accepted first. the program can be used to change the interrupt permission flags to change the hardware priority. the interrupt cycle shown in fig. 11-3 is a special cycle in which an interrupt request flag is reset, a vector address is specified, and the contents of the program counter are saved after an interrupt is accepted. the time required for an interrupt is equal to the time required for one instruction (2 m s, or 12 m s when the idc is operating). see section 11.4 for details. because the interrupt request flag is set to 1 regardless of the ei instruction and interrupt permission flags, an interrupt request can be identified by detecting an interrupt request flag using the program.
114 m pd17062 fig. 11-3 interrupt reception timing chart (1/2) (1) when one interrupt (e.g., rising edge at the int nc pin) is used (a) when an interrupt mask time is not set by the interrupt permission flag # # when the movt instruction or a normal instruction that does not satisfy the skip conditions is executed at interrupt acceptance $ $ when the movt instruction or an instruction satisfying the skip conditions is executed at interrupt reception (b) when an interrupt holding period is set by the interrupt permission flag instruction ei mov wr, #0001b poke intpm, wr inte int nc pin irqnc flag ipnc flag interrupt acceptance normal instruction interrupt cycle or 12 s 1 instruction cycle: 2 s interrupt permission period interrupt processing routine m m instruction ei mov wr, #0001b poke intpm, wr inte int nc pin irqnc flag ipnc flag interrupt processing routine movt dbf, @ar skip instruction interrupt cycle interrupt acceptance instruction ei mov wr, #0001b poke intpm, wr inte int nc pin irqnc flag ipnc flag interrupt acceptance interrupt cycle interrupt holding period interrupt processing routine
115 m pd17062 fig. 11-3 interrupt acceptance timing chart (2) when two or more interrupts (e.g., rising edge at the int nc pin and falling edge at the v sync pin) are used (a) hardware priorities (b) software priorities instruction ei mov wr, #0101b poke intpm, wr inte int nc pin irqvsyn flag ipnc flag ei ipvsyn flag irqnc flag v sync pin interrupt cycle interrupt cycle v sync pin interrupt acceptance int nc pin interrupt holding period int nc pin interrupt processing v sync pin interrupt processing v sync pin interrupt holding period int nc pin interrupt acceptance instruction ei mov wr, #0100b poke intpm, wr inte int nc pin irqnc flag ipnc flag ei ipvsyn flag irqnc flag v sync pin mov wr, #0101b poke intpm, wr int nc pin interrupt holding period v sync pin interrupt acceptance int nc pin interrupt processing int nc pin interrupt acceptance v sync pin interrupt holding period v sync pin interrupt processing interrupt cycle interrupt cycle
116 m pd17062 11.4 operations after interrupt acceptance when an interrupt is accepted, the following processing sequence is executed: (1) the interrupt enable flip-flop or interrupt request flag corresponding to the accepted interrupt is reset. in other words, a write protected state is set. (2) the stack pointer value is decreased by 1. (3) the contents of the program counter are saved in the address stack register indicated by the stack pointer. the contents of the program counter become the program memory address after the contents at interrupt acceptance. for a branch instruction, the contents become the branch destination address. for a subroutine call instruction, the contents become the called address. if a skip instruction satisfies the skip conditions, an interrupt is accepted after the next instruction is executed as the nop instruction. therefore, the contents of the program counter become the skipped address. (4) the lower two bits of the bank register (bank: address 79h) and the index enable flag (ixe: bit b 0 of address 7fh) are saved in the interrupt stack. (5) the contents of the vector address generator corresponding to the accepted interrupt are transferred to the program counter. in other words, processing is branched to the interrupt processing routine. the processing in (1) to (5) above is executed during one special instruction cycle (2 m s, or 12 m s when the idc is operating) without normal instruction execution. this instruction cycle is called the interrupt cycle. the processing from interrupt acceptance to branching to the corresponding vector address requires one instruction cycle. 11.5 returning control from interrupt processing routine to return control from the interrupt processing routine to the processing executed at interrupt acceptance, use the exclusive reti instruction. when the reti instruction is executed, the following processing sequence is executed. (1) the contents of the address stack register indicated by the stack pointer are restored in the program counter. (2) the contents of the interrupt stack are restored in the lower two bits of the bank register or bit b 0 of the index enable flag. (3) the stack pointer value is increased by 1. the processing in (1) to (3) above is executed during one instruction cycle of the reti instruction. the only difference between the reti instruction and subroutine return instruction ret or retsk is in the restoration of the contents of the bank register or index enable flag in (2) above.
117 m pd17062 11.6 interrupt processing routine an interrupt is accepted in a program area that permits interrupts regardless of the program being executed. therefore, to return control to the original program after interrupt processing, return the program to the state it is in when it is not processing an interrupt. for example, if an arithmetic operation is performed during interrupt processing, the contents of the carry flag may differ from those before interrupt acceptance. this content change may cause a decision error in the program to which control has returned. a system or control register that can at least operate within the interrupt processing routine should be saved or restored within the interrupt processing routine. see section 11.9 for processing that permits an interrupt while another interrupt is being processed (multiple interrupts). 11.6.1 save processing this section describes how to save the contents of registers using the interrupt routine as an example. only the contents of bank register and index enable flag of system registers are automatically saved by the hardware. use the program to save another system register as described in the example if necessary. the peek and poke instructions can be used to save or restore the contents of the system registers or other registers as described in the example. to save the contents of a register, a transfer instruction (ld r, ld m, st m, or st r) can be used in addition to peek and poke. if a transfer instruction is used to save the contents of a register when the row address of the general-purpose register is not defined at interrupt acceptance, the data memory address is hard to specify. if the general-purpose register address is not defined when the transfer instruction is used to save the contents of the general-purpose register, the address to be saved also becomes undefined. in this case, use of the general-purpose register should be fixed at least in the interrupt permission routine. however, because the address of the register file controlled by the peek or poke instruction is specified regardless of the contents of the general-purpose register and because addresses 40h-7fh of the register file overlap with the bank data memory, each system register can be saved only by specifying the bank. in the example, the peek or poke instruction is used to save the contents of the window register and general-purpose register pointer. then, the general-purpose register is respecified to row address 07h of bank0 and the st instruction is used to save another system register. fig. 11-4 illustrates register content saving using the peek and poke instructions. 11.6.2 restoration processing this section describes an example of restoration. to restore the contents of a register, reverse the procedures for register saving explained in section 11.6.1 . because an interrupt is always accepted in an interrupt permitted state (ei state), the ei instruction must be executed before the reti instruction. the ei instruction sets the interrupt enable flip-flop to 1 after the next reti instruction is executed. therefore, control is returned to the program before an interrupt is accepted, then the program enters an interrupt permitted state.
118 m pd17062 11.6.3 notes on interrupt processing routine note the following regarding the interrupt processing routine: (1) data saved by hardware all bank registers and index enable flags are reset to 0 after being saved in the interrupt stack. (2) data saved by software data saved by software is not reset after being saved. program status words such as the bcd flag, compare flag, carry flag, zero flag, and memory pointer enable flags keep their preacceptance values. initialize these program status words if necessary.
119 m pd17062 example saving the status in an interrupt processing routine ei m046 m047 m048 m04d m04e m05f btm0ck mem mem mem mem mem mem mem 0.46h 0.47h 0.48h 0.4dh 0.4eh 0.5fh 0.89h # poke $ peek % poke & mov ( st ) st m048, wr, m04e, rpl, m046, m047, wr rpl wr #0eh ar1 ar0 . . . * peek + st wr, m05f, btm0ck wr bank0 mov ld ld rpl, ar1, ar0, #0eh m046 m047 . . . ld poke wr, btm0ck, m05f wr . . . peek poke peek wr, rpl, wr, m04e wr m048 reti ei main routine program example interrupt processing routine (enters a di state) bank and ixe saving by hardware saving contents of required system register using software ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; restoration of contents of saved system registers interrupt reception interrupt processing saves the contents of the window register in m048. saves the contents of the general-purpose register pointer in m04e. sets row address 7 of bank 0 in the general-purpose register saves the contents of required system registers. saves the contents of the required control register. restores the contents of the saved control register. restores the contents of the general register-purpose pointer. restores the contents of the saved window register. the ei instruction permits an interrupt (inte setting) after the next reti instruction is executed. restoration by the bank or ixe hardware ; ; ; ; makes bank 0 available. sets row address 7 of bank 0 in the general-purpose register. restores the contents of the saved system registers. . . .
120 m pd17062 fig. 11-4 saving the system or control register using the window register numbers # to + correspond to the numbers in the program example. 0123456789abcdef 0 1 2 3 4 5 6 7 bank0 poke m048, wr ()# % + * ar1 ar0 wr rpl btm0ck $ & 0 1 2 3 column address data memory save area control register register file row address specify the general- purpose register.
121 m pd17062 11.7 external interrupts (int nc pin, v sync pin) there are two external interrupt sources: int nc and v sync . an interrupt request is issued when a rising or falling edge is input to the int nc or v sync pin. 11.7.1 configuration fig. 11-5 shows the configurations of the int nc and v sync interrupts. as shown in fig. 11-5, the int nc and v sync signals are input to the intnc or intvsyn latch and to edge detectors. the edge detectors output their respective interrupt request signals according to the inputs from the pin and the status of the iegnc or iegvsyn flip-flop. the iegnc flip-flop and iegvsyn flip-flop correspond to the iegnc flag and iegvsyn flag, respectively, in the interrupt edge selection register (intedge: address 1fh) of the control register. the intnc latch and intvsyn latch correspond to the intnc flag and intvsyn flag, respectively, in the interrupt-pin-level judge register (intjdg: address 0fh) of the control register. the schmitt triggers at the int nc and v sync inputs prevent pulses operations due to noise. these pins do not accept pulses of 1 m s or less. a minimum pulse width can be set for the int nc pin. see section 9.10 . fig. 11-5 int 0 pin and int 1 pin configurations irqnc irqvsyn intnc latch intvsyn latch iegvsyn flip-flop 0 fh 1 fh b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 0 i e g v s y n 0 i e g n c 0 i n t v s y n 0 i n t n c control register name address bit flag symbol interrupt edge select (intedge) interrupt pin level judge (intjdg) v sync pin int nc pin schmitt trigger iegnc flip-flop edge detection interrupt request block edge detection schmitt trigger
122 m pd17062 11.7.2 functions an interrupt can be issued when either a rising or falling edge is input to the int nc or v sync pin. use the iegnc or iegvsyn flag in the interrupt edge select register of the control register to select the rising or falling edge. table 12-2 shows the relationship between the iegnc and iegvsyn flags and the active edges of interrupt requests. note the following: if the iegnc or iegvsyn flag is used to switch the interrupt request edge, an interrupt request signal may be issued at the moment of switching. suppose that the iegnc flag is set to 0 (falling edge) and a high level is input to the int nc pin as shown in table 11-3. at this time, if the iegnc flag is set to 1, the edge detector determines that a rising edge has been input and therefore issues an interrupt request. see section 11.2 for operations after interrupt request issuance. because the signals input to the int nc and v sync pins are input to the intnc and intvsyn latches as shown in fig. 11-5, the input signal levels can be detected by reading the intnc and intvsyn flags. because the intnc and intvsyn flags are set or reset regardless of interrupts, they can be used as 2-bit general-purpose input ports when the corresponding interrupt functions are not used. if interrupt is not permitted, the flags can be used as general-purpose ports that can detect a rising or falling edge by reading the interrupt request flags (irqnc or irqvsyn). however, because the interrupt request flags are not automatically reset in this case, they must be reset by the program. table 11-2 iegnc and iegvsyn flags and interrupt request issuance edges iegnc flag values intvsyn active edges of interrupt request pins v sync pin int nc pin 00 01 10 11 rise rise rise fall fall rise fall fall
123 m pd17062 iegnc or iegvsyn flag change int nc or v sync pin whether interrupt irqnc flag request is issued 1 ? 0 low not issued no change (fall) (rise) high issued set 1 ? 0 low issued set (rise) (fall) high not issued no change table 11-3 interrupt request issuance by iegnc flag change 11.8 internal interrupt (timer, serial interface) there are two types of internal interrupts: the timer interrupt and the serial interface interrupt. 11.8.1 timer interrupt the timer interrupt function can issue interrupt requests at a specified time interval. an interval of 100 ms, 20 ms, or 5 ms can be selected. see chapter 12 for details. 11.8.2 serial interface interrupt the serial interface interrupt function can issue an interrupt request when a serial out or serial in operation terminates. therefore, interrupt requests are mainly issued by the serial clock. see chapter 16 for details.
124 m pd17062 11.9 multiple interrupts the multiple interrupt function is used to process interrupt c or d while another interrupt from source a or b is being processed as shown in fig. 11-6. the interrupt depth at this time is called the interrupt level. note the following regarding the multiple interrupt function. (1) interrupt source priorities (2) interrupt level restriction by an interrupt stack (3) interrupt level restriction by the address stack register (4) system or control register saving see sections 11.9.1 to 11.9.4 for details. fig. 11-6 example of multiple interrupts main bd a b c interrupt level 2 main routine interrupt level 1
125 m pd17062 11.9.1 interrupt source priorities when using the multiple interrupt function, the priorities of interrupt sources must be determined. for example, if the interrupt sources are a, b, c, and d, the following priorities can be specified: a = b = c = d or a < b < c < d. if a = b = c = d, the main routine always accepts interrupts a, b, c, and d. however, if interrupt c is accepted, interrupts a, b, and d are inhibited, making the multiple interrupt function unusable. if the priorities are a < b < c < d, interrupt c should be processed with the first priority even if interrupt a or b is being processed. in this case, processing of interrupt d has the same priority as interrupt c. the priorities can be set to hardware or software priorities by using the interrupt permission flags. section 11.3 describes the hardware and software priorities. to determine priorities at multiple interrupts, interrupt sources a and b are assumed have no priority and source a is assumed to issue requests at 10 ms intervals. the interrupt processing time is assumed to be 4 ms. source b is assumed to issue requests at 2 ms intervals. lastly, the interrupt processing time is assumed to be 1 ms. under these conditions, if interrupt a is issued by an interrupt request from a while interrupt b is being processed, and the priorities of a and b are not determined, several interrupts from b will not be executed. because an interrupt is generally used for emergency processing, the a < b priority should be set in the program to prevent interrupt a while interrupt b is being processed and accept interrupt b while interrupt a is being processed. when using the multiple interrupt function for non-emergency purposes, priorities need not be determined. however, if the number of existing interrupt sources exceeds the multiple interrupt level limit described in section 11.9.2 or 11.9.3 , be sure to determine priorities so that the interrupt level is not exceeded. 11.9.2 interrupt level restriction by interrupt stack the contents of the bank register of the system register and index enable flag are automatically saved in the interrupt stack. fig. 11-7 (a) shows the interrupt stack operation. the contents of all bank registers and index enable flags are reset when they are saved in the interrupt stack. because there are two levels of interrupt stacks, if multiple interrupts of more than two levels are issued, the contents of the bank register and index enable flag are not restored normally as shown in fig. 11-7 (b). in other words, multiple interrupts of more than two levels cannot be used. however, if the bank register and index enable flag are fixed in a main routine permits interrupts and multiple interrupts have clear priorities as shown in fig. 11-8, multiple interrupts of two levels or more can be used by using subroutine return instruction ret.
126 m pd17062 for multiple interrupts of more than two levels, operations of the device and emulator differ as shown in figs. 11-8 and 11-9. at interrupt stack, the device operation is the sweep-off type and the emulator operation is the rotation type. use the ret instruction as the last restoration instruction when using multiple interrupts of more than two levels. reti and ret instructions operate in the same manner except when restoring the contents of the interrupt stack.
127 m pd17062 fig. 11-7 interrupt stack operation at multiple interrupts (a) multiple level-2 interrupts (b) multiple level-3 interrupts main a main b a main reti reti a main main main main main interrupt b interrupt stack undefined main routine interrupt a interrupt stack undefined undefined main a main b a c b a main b a a a reti reti reti a a a a if control is returned to the main routine at this time, bank and ixe of interrupt a are restored and the main routine operates abnormally. undefined undefined main routine interrupt a interrupt b interrupt c undefined
128 m pd17062 main a main b a c b a main b a a a reti reti ret a a a a bank0 clr1 ixe di bank0 clr1 ixe ei undefined undefined main routine interrupt a interrupt b interrupt c undefined fig. 11-8 example of using multiple level-3 interrupts to interrupt a, be sure to set a lower priority than interrupts b and c. fix the bank register and index enable flag (bank0 and ixe = 0 in this example) in the main routine that permits interrupt a. this processing enables the use of ret instructions for multiple interrupts of three levels after specifying the bank register and index enable flag of the main routine. if the bank register and index enable flag at interrupt a are exactly the same as those of the main routine, the reti instruction can be used. however, because the operation of the 17k series emulator differs as shown in fig. 11-9, the reti instruction cannot be used for debugging.
129 m pd17062 fig. 11-9 interrupt stack operation when 17k series emulator is used if the reti instruction is used on the emulator, the contents of the bank register and index enable flag of interrupt b are restored. main main a b a c b a main b b b b reti reti ret a a a a undefined undefined main routine interrupt a interrupt b interrupt c undefined
130 m pd17062 11.9.3 interrupt level restriction by address stack register the return address at control return from interrupt processing is automatically saved in the address stack register. the address stack register can use the six levels from asr0 to asr5 as described in chapter 4 . because the interrupt sources are the int nc pin, timer, v sync pin, and serial interface, the multiple interrupt level is unlimited when the address stack register is used only for interrupts. however, because the address stack register is also used to save the return address at subroutine calling, multiple interrupt levels are limited according to the levels of the address stack register used for subroutine calling. for example, if four levels are used for subroutine calling, only two levels of the multiple interrupts shown in fig. 11-10 can be used. fig. 11-10 address stack register operation asr0 asr1 asr2 asr3 asr4 asr5 asr6 asr7 undefined undefined undefined undefined undefined main undefined undefined undefined undefined sub1 main undefined undefined undefined sub2 sub1 main undefined undefined sub3 sub2 sub1 main undefined aaa sub3 sub2 sub1 main sub4 aaa sub3 sub2 sub1 main sub4 aaa sub3 sub2 sub1 main undefined undefined undefined undefined undefined undefined sub4 aaa sub3 sub2 sub1 main ret bbb: sub4: aaa: sub3: sub2: sub1: main: level 0 level 1 level 2 level 3 level 4 level 5 level 6 level 7 level 8 stack pointer sp main routine subroutine 1 subroutine 2 subroutine 3 interrupt a subroutine 4 interrupt b subroutine 5 because the contents of the address stack register (asr0) are always undefined when the stack pointer is 0, the return addressof the ret instruction also becomes undefined. address stack register
131 m pd17062 11.9.4 saving the contents of system and control registers the contents of system and control registers must be saved before using the multiple interrupt function. the contents of these registers change during interrupt processing. an area must be obtained for these contents for each interrupt source. an interrupt being accepted and interrupts with lower priorities must be inhibited, and interrupts with higher priorities must be permitted. because an interrupt with a high priority is an emergency interrupt, it should have first priority. therefore, the contents of system and control registers should be saved after permitting an interrupt with a high priority. the following example describes processing of the interrupt processing routine to enable an interrupt with a high priority and to save the contents of system and control registers: example example of permitting an interrupt and saving register contents at multiple interrupts use the int nc pin, v sync pin, and timer interrupts with the following software priorities: v sync pin > timer > int nc pin a timer interrupt is assumed to be accepted in the first level. the figure below shows an example program and flowchart for this processing. flowchart program example # $ % & ( ) * + , ei reti ei ei di mov poke bank1 poke peek poke mov poke peek poke peek poke peek poke peek wr, intpm, #0111b wr wr intpm wr #0100b wr wr, m3, wr, intpm, m2 wr m1 wr, intpm, wr, m3 wr rpl wr m1, wr, m2, wr, intpm, v sync , int nc , and timer interrupt permission ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; (built-in macro) ; bank specification window register saving interrupt permission flag saving permission of interrupt with high priority system register saving interrupt processing system register restoration interrupt permission flag restoration window register restoration permit timer, int nc pin, and v sync pin interrupts using the interrupt permission register. the contents of the bank register, index enable flag, and program counter are automatically saved. restore the contents of the interrupt permission register. restores the contents of the window register. restore the contents of system and control registers other than window and interrupt permission registers. save the contents of system and control registers other than window and interrupt permission registers. saves the window register. save the interrupt permission register in data memory m2. permit a v sync pin interrupt using the interrupt permission register. specifies that the data is saved in bank1. timer interrupt main routine
132 m pd17062 in # , specify the data memory bank containing the contents of the system register. because the bank becomes bank0 when an interrupt is accepted, if the data is saved in bank0, this instruction is not necessary. in $ , save the contents of the window register in data memory m1. because the poke instruction is used, the address of data memory m1 should be 40h or more. because the window register is used as a work area for subsequent data saving, its contents must be saved first. in % , save the interrupt permission flags (ipnc, ipbmt0, and ipvsyn) set when interrupts are accepted. in this example, all int nc pin, v sync pin, and timer interrupts must be permitted when control is returned to the main routine in this save operation. the priority of the timer interrupt is higher than that of the int nc pin. therefore, if the timer interrupt is accepted while the int nc pin interrupt is being processed, control should be returned with the int nc pin interrupt inhibited. in & , permit v sync interrupt with a lower priority than the timer interrupt. then, use the ei instruction to permit all interrupts. because processing in # , $ , % , and & must be executed with an interrupt inhibited, the v sync interrupt with the highest priority is also inhibited during this processing. in ( and ) , save and restore the contents of the system and control registers. at this time, interrupts with high priorities can be enabled. if the contents of the registers are saved when a v sync interrupt with a high priority is accepted, the contents of the system and control registers do not change when control is returned from v sync interrupt processing. in * and + , return the contents of the interrupt permission flag and window register. at this time, all interrupts should be inhibited. if a timer interrupt is issued when the instruction in * that permits an interrupt is executed in an ei state, the contents of the window register in + are not restored but are saved again in $ . at this time, the contents of the window register cannot be restored.
133 m pd17062 12. timer the timer functions are used to manage the time in creating programs. 12.1 timer configuration fig. 12-1 shows the configuration of the timer. the timer consists of two blocks, timer carry flip-flop (timer carry ff) block and timer interrupt block, as shown in fig. 12-1. the clock generation circuit, which specifies time intervals for the timer carry ff and timer interrupts, consists of an 8 mhz frequency divider, selector a, selector b, bias circuit, and a timer mode select register (btm0ck at address 09h), which is a control register. 12.1.1 timer carry ff block configuration the timer carry ff block consists of selector a, timer carry ff, a timer carry ff judge register (btm0cyjdg at address 17h), which is a control register, as shown in fig. 12-1. 12.1.2 timer interrupt block configuration the timer interrupt block consists of selector b, an interrupt control block, an interrupt permission register (intpm at address 2fh), which is a control register, and an interrupt request register (intreq at address 3fh), as shown in fig. 12-1. fig. 12-1 timer configuration 09h 2fh 3fh 17h b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b t m 0 z x b t m 0 c k 2 b t m 0 c k 1 b t m 0 c k 0 i p s i o 0 i p v s y n i p b t m 0 i p n c i r q s i o 0 i r q v s y n i r q b t m 0 i r q n c 000 b t m 0 c y 10 hz 50 hz 200 hz 8 mhz 50/60 hz 100 ms (10 hz), 20 ms (50 hz), or 5 ms (200 hz) can be selected. control register register address bit flag symbol timer mode select (btm0ck) interrupt permission (intpm) interrupt request (intreq) timer carry ff judge (btm0cyjdg) selector b interrupt control block interrupt request signal frequency divider timer interrupt block selector a timer carry ff bias timer carry ff block
134 m pd17062 12.2 timer functions there are two timer functions, timer carry ff check and timer interrupt. the timer carry ff check function performs time management by checking, by program, the state of the timer carry ff, which is set at constant intervals. the timer interrupt function performs time management by requesting an interrupt at constant intervals. the timing at which the timer carry ff is set to 1 or the timer interrupt is requested is controlled by the timer interval set pulse output from selector a or b, respectively. the timer interval set pulse can be specified as 10 hz (100 ms), 50 hz (20 ms), or 200 hz (5 ms) by setting the appropriate data in the timer mode select register. the timer mode select register is used to specify the time base mode (internal timer mode or external timer mode) for selectors a and b. the internal timer mode uses pulses generated by dividing the devices operating frequency (8 mhz). the external timer mode uses 50 or 60 hz supplied at the p0b 2 /tmin pin. the timer mode select register is again used to specify whether to divide the frequency of the pulse supplied at the p0b 2 /tmin pin by 5 or 6. the timer interval set pulse is specified by combining the timer carry ff and timer interrupt. fig. 12-2 shows the relationships between the timer mode select register and timer interval set pulse. in the internal timer mode, the timer interval set pulse is generated by dividing the devices operating frequency (8 mhz). if the frequency deviates from the correct value (8 mhz), the timer interval set pulse will also deviate at the same ratio.
135 m pd17062 fig. 12-2 relationship between the timer mode select register and timer interval set pulse b 3 b 2 b 1 b 0 b t m 0 z x b t m 0 c k 2 b t m 0 c k 1 b t m 0 c k 0 09h r/w read/write 000 001 010 011 100 101 110 111 0 1 10 hz ( 100 ms) 200 hz ( 5 ms) 10 hz ( 100 ms) 200 hz ( 5 ms) f tmin /5 hz (5/f tmin s) 200 hz ( 5 ms) f tmin /6 hz (6/f tmin s) 200 hz ( 5 ms) 200 hz ( 5 ms) 10 hz ( 100 ms) 50 hz ( 20 ms) 50 hz ( 20 ms) 200 hz ( 5 ms) f tmin /5 hz (5/f tmin s) 200 hz ( 5 ms) f tmin /6 hz (6/f tmin s) 200 hz 50 hz f tmin /6 (hz) 10 hz f tmin /5 (hz) control register register address bit flag symbol timer mode select (btm0ck) selection of frequency (time) of the timer carry ff set pulse selection of frequency (time) of the timer interrupt pulse internal timer internal timer internal timer internal timer external timer internal timer external timer internal timer internal timer internal timer internal timer internal timer internal timer external timer internal timer external timer f tmin is the input frequency (50 or 60 hz) at the p0b 2 /tmin pin. disables the bias circuit. enables the bias circuit. duty cycle duty cycle 80 ms 1 ms 5 ms 4 ms 100 ms 20 ms 20% 80% 50% 10 ms 20 ms 10 ms 50%
136 m pd17062 12.3 timer carry flip-flop (timer carry ff) the timer carry ff is set to 1 by the positive-going edge of the timer carry ff set pulse specified by the timer mode select register. the content of the timer carry ff corresponds to the lowest bit (btm0cy flag) of the timer carry ff judge register on a one-to-one basis, and when the timer carry ff is set to 1, the btm0cy flag is also set to 1 at the same time. the btm0cy flag is reset to 0 by the peek instruction when it reads the content of the window register (read & reset). when the btm0cy flag is reset to 0, the timer carry ff is also reset to 0 at the same time. reading the btm0cy flag by program can create a timer that operates at intervals of the time specified in the timer mode select register. section 12.3.1 gives an example of a program used to read the btm0cy flag. when using the timer carry ff, observe the following point. a power-on reset disables the timer carry ff from being bet. it cannot be set until the peek instruction is issued to read the content of the btm0cy flag. 0 is read in when the btm0cy flag is read-accessed for the first time after a power-on reset. once it is reset, the timer carry ff is set to 1 at intervals of the time specified in the timer mode select register. the timer carry ff also controls the timing of a ce reset. to put in another way, once the ce pin goes from a low to a high, a ce reset occurs at the same time the timer carry ff is set. therefore, reading the content of the btm0cy flag at a reset (power-on or ce reset) enables a power failure check. see section 12.4 and chapter 14 for details. because the btm0cy flag is a read-only flag, writing to it with the poke instruction does not affect the operation of the device at all. however, an error is reported by the 17k series assembler.
137 m pd17062 12.3.1 example of using the timer based on the btm0cy flag an example of a program follows. example initflg not btm0zx, not btm0ck2, not btm0ck1, not btm0ck0 ; built-in macro ; specifies that the timer carry ff be set at intervals of 100 ms. loop1: mov m1, #0110b loop2: skt1 btm0cy ; built-in macro ; tests the btm0cy flag. branches to next if the flag is 0. br next add m1, #0100b ; adds 4 to data memory m1. skt1 cy ; built-in macro ; tests the cy flag. br next ; branches to next if the flag is 0. process a ; performs process a if the flag is 1. mov m1, #0110b next: process b ; performs process b and branches to loop. br loop this program performs process a at intervals of one second. note the following point (1) when creating this program. (1) the time interval at which the btm0cy flag is checked must be less than the time interval at which the timer carry ff is set to 1. this is because if it takes 100 ms or longer to perform process b, it is impossible to detect when the timer carry ff is set, as shown in fig. 12-3. fig. 12-3 btm0cy flag check and timer carry ff #$% &( skt1 btm0cy skt1 btm0cy skt1 btm0cy timer carry ff set pulse btm0cy flag process b process b' because it takes long to perform process b' after it is detected that the btm0cy flag is set at $ , it is impossible to detect when the btm0cy flag is set at % .
138 m pd17062 12.3.2 timer error caused by the btm0cy flag there are two types of timer error that can occur because of the btm0cy flag. one type depends on the timing when the btm0cy flag is checked, and the other type occurs when the timer carry ff setting interval is changed. these types of timer error are detailed below. (1) timer error by btm0cy flag check timing as described in section 12.3.1 , the time interval at which the btm0cy flag is checked must be less than the time interval at which the timer carry ff is set to 1. suppose the time interval at which the btm0cy flag is checked is t check , and the time interval (100 ms or 5 ms) at which timer carry ff is set is t set . the relationship between these two intervals must be as follows: t check < t set under this condition, as shown in fig. 12-4, the timer error that depends on the timing when the btm0cy flag is checked is as follows: 0 < error < t check fig. 12-4 timer error that depends on the time interval at which the btm0cy flag is checked as shown in fig. 12-4, when the btm0cy flag is checked at $ , it appears to be 1 and causes the timer to be updated. when it is checked at % , it appears to be 0, and defers the updating of the timer until it is checked again at & . in this case, the timer count is increased by t check3 . skt1 btm0cy # skt1 btm0cy $ skt1 btm0cy % skt1 btm0cy & timer carry ff set pulse btm0cy flag t set t check t check2 t check3
139 m pd17062 (2) timer error that occurs when the timer carry ff setting time interval is changed the timer carry ff setting time interval is specified by the btm0ck2, btm0ck1, and btm0ck0 flags in the timer mode select register. as shown in fig. 12-1 and 12-2, the timer interval set pulse can be selected from 200 hz, 10 hz, and an external timer. these three pulses operate independently. therefore, when the timer interval set pulse is switched using the btm0ck2, btm0ck1, or btm0ck0 flag, a timer error occurs as shown in the following example. example ; # initflg not btm0zx, not btm0ck2, not btm0ck1, not btm0ck0 ; built-n macro process a ; specifies the timer carry ff set pulse as 10 hz (100 ms). ; $ set1 btm0ck0 ; built-in macro ; specifies the timer carry ff set pulse as 200 hz (5 ms). process a ; % clr1 btm0ck0 ; built-in macro ; specifies the timer carry ff set pulse as 10 hz (100 ms). with this coding, the timer carry ff set pulse is switched as shown below. # $ set1 btm0ck0 % clr1 btm0ck0 skt1 btm0cy internal pulse 10 hz internal pulse 200 hz timer carry ff set pulse btm0cy flag as shown above, when the timer carry ff setting time interval is switched, if a newly selected pulse goes low, it allows the btm0cy flag to preserve its previous state ( $ in the figure). if the pulse goes high, it sets the btm0cy flag to 1 ( % in the figure).
140 m pd17062 as shown in fig. 12-5, if the timer carry ff setting time interval is switched, the timer error that occurs before the btm0cy flag is set for the first time is as follows: -t set < error < t check where t set : newly selected timer carry ff setting time interval t check : time interval at which the btm0cy flag is checked the internal pulses, 4 hz, 10 hz, 200 hz, and 1 khz, have a phase difference. however, this phase difference is less than a newly selected set pulse interval, and included in the timer error described above. see section 12.6 for details about the phase difference of each pulse. fig. 12-5 timer error that occurs when the timer carry ff setting time interval is switched from a to b (a) timer error of -t set (b) timer error of t check t set t set = 0 skt1 btm0cy internal pulse a internal pulse b timer carry ff set pulse btm0cy flag true timer interval actual timer interval time interval switched here if the btm0cy flag is checked right after the timer setting time interval is switched, it appears to be 1, and therefore, the timer error is -t set . actual timer interval true timer interval time interval switched here if the timer setting time interval is switched right after the btm0cy flag is checked, the btm0cy flag remains reset for one cycle, and therefore, the timer error is t check . . . = 0 . . t check
141 m pd17062 12.4 cautions in using the timer carry ff the timer carry ff is used not only as a timer function but also as a reset sync signal at a ce reset. a ce rest occurs when the timer carry ff set pulse rises after the ce pin goes from a low to a high. note the following points: (1) the sum of the time used to update the timer and the time interval at which the btm0cy flag is checked must be less than the timer carry ff setting time interval. (2) if a created program needs a timer that operates at constant intervals regardless of a ce reset once a power- on reset occurs, the program must correct the timer at each ce reset. (3) a check of the btm0cy flag takes precedence over a reset sync signal for a ce reset. if both occur at the same time, a ce reset is delayed one cycle. sections 12.4.1 to 12.4.3 detail the above topics.
142 m pd17062 12.4.1 timer update time and btm0cy flag check time interval as described in section 12.3.1 , the time interval t set at which the btm0cy flag is checked must be less than the time interval at which the timer carry ff is set. even when the above requirement is satisfied, if the timer update process takes long, the timer process may not be performed correctly when a ce reset occurs. to solve this problem, it is necessary to satisfy the following condition. t check + t timer < t set where t check : time interval at which the btm0cy flag is checked t timer : timer update process time t set : time interval at which the timer carry ff is set an example follows: example timer update process and btm0cy flag check time interval start: ; program address 0000h initflg not btm0zx, not btm0ck2, not btm0ck1, not btm0ck0 ; built-in macro ; specifies the timer carry ff setting time interval as 100 ms. timer: ; # skt1 btm0cy flag ; built-in macro ; tests the btm0cy flag. br aaa ; branches to aaa, if 0. timer update br timer aaa: process a br timer the timing chart for the processing by the above program is shown below. skt1 btm0cy skt1 btm0cy ce pin timer carry ff set pulse btm0cy flag btm0cy flag check time interval t check timer update processing t timer if this processing takes long, a ce reset occurs before the processing is completed. ce reset
143 m pd17062 12.4.2 correcting the timer carry ff at a ce reset this section describes an example of correcting the timer at a ce reset. if the timer carry ff is used both to check for power failure and as a timer, it is necessary to correct the timer at a ce reset, as explained in the following example. the timer carry ff is reset to 0 at a power-on reset, and it is kept from being set until the btm0cy flag is read-accessed using a peek instruction. when the ce pin goes from a low to a high, a ce reset occurs in synchronization with the positive-going edge of the timer carry ff set pulse. at this point, the btm0cy flag is set to 1 and becomes active. therefore, checking the state of the btm0cy flag at a system reset (power-on reset or ce reset) can discriminate between a power-on reset and ce reset; if the flag is 0, it indicates a power-on reset, and if 1, it indicates a ce reset (power failure check). a timer for ordinary time measurement must continue to operate even at a ce-reset. reading the btm0cy flag for a power failure check could reset the btm0cy flag to 0, thus losing a chance of detecting a set (1) state of the flag. to skirt the above problem, it is necessary to update the timer for time measurement at a ce reset that occurs because of power failure. see also section 14.6 for details about a power failure check. example correcting the timer at a ce reset when using the timer carry ff for a power failure check and clock update start: ; program address 0000h process a ; # skt1 btm0cy ; built-in macro ; tests the btm0cy flag. br initial ; branches to initial if 0 (power failure check) backup: ; $ update the clock by 100 ms ; correct the clock because of a backup (ce reset). loop: ; % process b ; while performing process b, skf1 btm0cy ; tests the btm0cy flag and updates the clock. br backup br loop initial: initflg not btm0zx, not btm0ck2, not btm0ck1, not btm0ck0 ; built-in macro ; because a power failure (power-on reset) is detected, the timer ; carry ff setting time interval is set to 100 ms, and passes ; control to process c. process c br loop fig. 12-6 shows the timing chart for the above program.
144 m pd17062 fig. 12-6 timing chart as shown in fig. 12-6, the positive-going edge of the internal 10 hz pulse starts the program at 000h at a power-on reset. when the btm0cy flag is checked at point a, it appears to be reset to 0, thus indicating a power-on reset, because it is just after the power is turned on. when a power-on reset occurs, process c is performed to specify the timer carry ff set pulse as 100 ms. because the timer carry ff was read-accessed once at point a, the btm0cy flag is set to 1 at intervals of 100 ms. even when the ce pin goes low at point b and high at point c, the program continues updating the clock while performing process b unless a clock stop instruction has been executed. because the ce pin goes from a low to a high at point c, a ce reset occurs at point d, where the timer carry ff set pulse rises for the second time, thus starting the program at 0000h. when the btm0cy flag is checked at point e, a backup (ce reset) is detected because the btm0cy flag is already set to 1. as seen from the timing chart, if the clock is not updated by 100 ms at point e, the clock loses 100 ms each time a ce reset occurs. if process a (power failure check) takes longer than 100 ms at point e, the program loses twice a chance of detecting when the btm0cy flag is set; therefore, process a must be completed within 100 ms. to put in another way, checking the btm0cy flag for power failure must be performed before the timer carry ff is set after the program starts at 0000h. ac b b b bb bb bbb a bbb %% %%% %% %% # %% 5 v 0 v v dd ce internal pulse 10 hz timer carry ff set pulse btm0cy flag program processing program instruction supply voltage applied start at address 0 on a power-on reset timer incre- mented timer incre- mented timer incremented timer incremented timer incremented btm0cy flag detected start at address 0 on a ce reset timer updated because the btm0cy flag has been detected to be set to 1 point a point b point c point d point e #%
145 m pd17062 12.4.3 if the btm0cy flag is checked at the same time with a ce reset as described in section 12.4.2 , a ce reset occurs at the same time the btm0cy flag is set to 1. if the btm0cy flag read instruction happens to occur at the same time a ce reset occurs, the btm0cy flag read instruction takes precedence. once a ce pin goes from a low to a high, if the setting of the btm0cy flag (at the positive-going edge of the timer carry ff set pulse) and a btm0cy flag read instruction occur at the same time, a ce reset occurs next time the btm0cy flag is set. this operation is shown in fig. 12-7. fig. 12-7 operation that occurs when a ce reset and a btm0cy flag read instruction coincide so, if your program checks the btm0cy flag cyclically and the btm0cy flag check time interval coincides with the btm0cy flag setting time interval, a ce reset will not occur forever. note the following point: because one instruction cycle is 2 m s (1/500 khz), a program that checks the btm0cy flag once at every 500 instructions reads the btm0cy flag at every 1 ms (2 m s 500). under this condition, whichever timer interval set pulse, 5 ms or 100 ms, is selected, a ce reset will not occur for ever, once the setting and checking of the btm0cy flag occur at the same time. to be specific, avoid creating a cyclic program that satisfies the following condition. t set 500 = n (n is any integer) x where t set : btm0cy flag setting time interval x : btm0cy flag read instruction cycle time x number of steps in other words, the program should not contain x steps when the above calculation produces any integer. skt 1 btm0cy skt 1 btm0cy ce reset skt1 btm0cy (peek ) (skt ) ce pin timer carry ff set pulse btm0cy flag timer carry ff set pulse btm0cy flag instruction built-in macro 2 s if the btm0cy flag is read during this period, a ce reset is deferred by one cycle. normally, the program starts at address 0000h at this point, but a ce reset does occur because the program to read the btm0cy flag also happens to run. peek wr, . mf. btm0cy shr 4 skt wr, #, df. btm0cy and 000fh m
146 m pd17062 the program shown below is an example of a program that meets the above condition. do not creates such a program. example process a initflg not btm0zx, not btm0ck2, not btm0ck1, btm0ck0 ; built-in macro ; specifies the timer carry ff set pulse as 5 ms. loop: ; # skt1 btm0cy ; built-in macro br bbb aaa: 496 steps br loop bbb: 496 steps br loop because the btm0cy flag read instruction at # in this program is executed at every 500 instructions, once the btm0cy flag happens to be set at the timing of the instruction at # , a ce reset will not occur forever. in addition, because the instruction execution time is 12 m s (1/83.33 khz) during the operation of the idc, do not create a cyclic program that meets the following condition. t set 83.33 = n (n is any integer) x where t set : btm0cy flag setting time interval x : btm0cy flag read instruction cycle time x number of steps
147 m pd17062 12.5 timer interrupt the timer interrupt function issues an interrupt request at the negative-going edge of the timer interrupt pulse specified in the timer mode select register. the timer interrupt request corresponds to the irqbtm0 flag in the interrupt request register on a one-to- one basis. when an interrupt is requested, the corresponding irqbtm0 flag is set to 1. in other words, when a timer interrupt request pulse falls, the irqbtm0 flag is set to 1. as described in chapter 11 , to use the timer interrupt function, it is necessary not only to issue an interrupt request but also to execute the ei instruction, which enables all interrupts, and enable the timer interrupt. the timer interrupt is enabled by setting the ipbtm0 flag to 1 in the interrupt permission register. to put in another way, if the ei instruction has been executed, and the ipbtm0 flag is set to 1, an interrupt request is accepted when the irqbtm0 flag is set to 1. when a timer interrupt request is accepted, program control is passed to program memory address 0003h. when the interrupt request is accepted, the irqbtm0 flag is reset to 0. fig. 12-8 shows the relationship between the timer interrupt pulse and the irqbtm0 flag. fig. 12-8 relationship between the timer interrupt pulse and the irqbtm0 flag # irqbtm0 ipbtm0 inte ff ei di timer interrupt pulse the negative-going edge of the timer interrupt pulse sets the irqbtm0 flag. the ei instruction is executed, but the interrupt request is not accepted because the ipbtm0 flag is not set. the timer interrupt request is accepted at the same time the ipbtm0 flag is set. timer interrupt request accepted interrupt pending interrupt enabled at this point, note the following: once the irqbtm0 flag is set when a timer interrupt is disabled by the di instruction or the ipbtm0 flag, the corresponding interrupt request is accepted immediately when the ei instruction is executed or the ipbtm0 flag is set. in the above case, writing 0 to the irqbtm0 flag can cancel the interrupt request. meanwhile, writing 1 to the irqbtm0 flag amounts to issuing an interrupt request. accepting a timer interrupt request uses one level of stack. when an interrupt request is accepted, the contents of the bank register and index enable flag are saved automatically. a reti instruction is used to return from an interrupt handling routine. this instruction is dedicated to use for this purpose. see chapters 4 and 11 for details. sections 12.5.1 and 12.5.2 describe an example of using a timer interrupt and a timer interrupt error, respectively. see chapter 11 for relationships with other types of interrupts (int nc pin, v sync pin, and serial interface).
148 m pd17062 12.5.1 example of using a timer based on a timer interrupt an example follows. example br aaa ; branches to aaa. timer: ; program address 0003h add m1, #0001b ; add 1 to m1. skt1 cy ; tests the cy flag. br bbb ; returns if no carry is generated. process a bbb: ei reti aaa: initflg not btm0zx, not btm0ck2, not btm0ck1, not btm0ck0 ; built-in macro ; specifies the timer interrupt pulse as 5 ms. mov m1, #0000b ; clears the content of m1 to 0. set1 ipbtm0 ; enables a timer interrupt. ei ; enables all types of interrupts. loop: process b br loop this program performs process a at every 80 ms. at this point, note the following: accepting an interrupt request causes a di state automatically, and the irqbtm0 flag is set to 1 even in the di state. in other words, if process a takes 5 ms or longer, an interrupt request will be accepted immediately when a return is made by a reti instruction, thus disabling process b from being performed.
149 m pd17062 12.5.2 timer interrupt error as explained in section 12.4 , an interrupt request is accepted each time the timer interrupt pulse goes low, provided that the interrupt is enabled. a timer error due to use of a timer interrupt occurs when: (1) an interrupt request is accepted for the first time after the timer interrupt is enabled. (2) an interrupt request is accepted for the first time after the timer interrupt pulse interval is switched. (3) writing to the irqbtm0 flag occurs. these timer error types are illustrated in fig. 12-9. fig. 12-9 timer interrupt error (1/2) (a) when a timer interrupt is enabled irqbtm0 ipbtm0 inte ff ei di t set ei ei ei # $ % set1 ipbtm0 timer interrupt pulse interrupt pending interrupt request accepted interrupt request accepted interrupt request accepted at point # , an interrupt request is accepted immediately when the ipbtm0 flag is set to enable the timer interrupt. in the above case, timer error -t set occurs. if the ei instruction is executed at point $ to enable interrupts, an interrupt occurs at the negative-going edge of the timer interrupt pulse at point % . in the above case, the time error is: -t set < timer error < 0
150 m pd17062 fig. 12-9 timer interrupt error (2/2) (b) when the timer interrupt pulse is switched ei # ei ei ei % $ irqbtm0 ipbtm0 inte ff ei di internal pulse a internal pulse b timer interrupt pulse interrupt accepted timer interrupt pulse switched interrupt accepted timer interrupt pulse switched interrupt accepted although the timer interrupt pulse is switched to b at # , no interrupt occurs because the timer interrupt pulse does not go low. therefore, an interrupt occurs when the interrupt pulse goes low at point $ . when the timer interrupt pulse is switched to a at point % , the timer interrupt pulse goes low, and the interrupt request is accepted immediately. (c) when the irqbtm0 flag is manipulated ei ei ei # irqbtm0 ipbtm0 inte ff ei di $ timer interrupt pulse interrupt accepted set1 irqbtm0 interrupt accepted clr1 irqbtm0 no interrupt accepted interrupt accepted when the irqbtm0 flag is set at point # , an interrupt request is accepted immediately. if the irqbtm0 flag is reset at the same time the timer interrupt pulse goes low at point $ , the interrupt request is not accepted.
151 m pd17062 12.6 cautions in using the timer interrupt in a program using a timer that operates at constant intervals once a power-on reset occurs, it is necessary to have the timer interrupt handling routine finish within that constant interval. this is explained using an example. example br aaa ; branches to aaa after reset. timer: ; program address 0003h add m1, #0100b ; adds 0100b to the content of m1. skt1 cy ; performs clock processing if a carry occurs. br aaa ; # clock process ei reti aaa: initflg not btm0zx, not btm0ck2, not btm0ck1, not btm0ck0 ; built-in macro ; specifies the timer interrupt time and timer carry ff setting time interval as 250 and 100 ms, respectively. set1 ipbtm0 ; built-in macro ei ; enables the timer interrupt. process a br aaa the program in this example performs the clock process # at every one second while performing process a. if the ce pin goes from a low to a high as shown in fig. 12-10 (a), a ce reset occurs in synchronization with the positive-going edge of the timer carry ff set pulse. if the timer interrupt request happens to be issued simultaneously when the timer carry ff is set, a ce reset takes precedence. when the ce reset occurs, it resets the timer interrupt request (irqbtm0 flag), thus skipping the timer process once.
152 m pd17062 in reality, however, to avoid skipping the timer process in the above example, a delay is provided between the negative-going edge of the timer carry ff set pulse and the negative-going edge of the timer interrupt pulse, as shown in fig. 12-10 (b). as shown at (2) in fig. 12-10, restricting the clock process to within 10 ms can eliminate skipping of a timer interrupt that would otherwise be caused by a ce reset. fig. 12-10 timing chart (a) (b) ce pin timer carry ff set pulse timer interrupt pulse timer interrupt because the timer carry ff set pulse goes high, a ce reset occurs here, thus skipping detection of a timer interrupt once. ce pin timer carry ff set pulse timer interrupt pulse timer interrupt timer interrupt delay; 10 ms in this case ce reset because there is a delay of 10 ms between the negative-going edge of the timer interrupt pulse and the positive-going edge of the timer carry ff set pulse, a ce reset does not hamper the normal timer processing, provided that the timer interrupt handling is finished within 10 ms.
153 m pd17062 13. standby the standby function is intended to reduce the current drain of the device at backup. 13.1 standby block configuration fig. 13-1 shows the configuration of the standby block. as shown in fig. 13-1, the standby block is further divided into halt control and clock stop control blocks. the halt control block consists of the halt control circuit, interrupt control block, timer carry ff, and the p0d 0 / adc 2 to p0d 3 /adc 5 pins. it controls the operation of the cpu (program counter, instruction decoder, and alu block). the clock stop control block controls the 8 mhz crystal oscillator, cpu, system register, and control register. fig. 13-1 standby block configuration alu halt block interrupt block timer carry ff halt control circuit halt h p0d 3 /adc 5 pin p0d 2 /adc 4 pin p0d 1 /adc 3 pin p0d 0 /adc 2 pin input latch program counter (pc) instruction decoder clock stop block system register ce pin clock stop control circuit stop s control register x out pin x in pin internal clock cpu
154 m pd17062 13.2 standby function the standby function stops the whole or part of the operation of the device to reduce its current drain. the standby function is divided into halt and clock stop functions. the halt function uses a dedicated instruction (halt h instruction) to stop the cpu in order to reduce the required current drain. the clock stop function uses a dedicated instruction (stop s instruction) to stop the 8 mhz crystal oscillator in order to reduce the current drain in the device. to use these functions, it is necessary to specify a device operation mode at the ce pin. section 13.3 explains the device operation mode specified at the ce pin. sections 13.4 and 13.5 describe the halt and clock stop functions. remark for the m pd17062, the operand s of the stop s instruction must be 0000b. therefore, the actual instruction is: stop 0000b
155 m pd17062 13.3 device operation mode specified at the ce pin the ce pin controls the following items according to the level and positive-going edge of its input signal. (1) whether to enable or disable the clock stop instruction (2) whether to reset the device sections 13.3.1 and 13.3.2 explain the above items, respectively. 13.3.1 controlling whether to enable or disable the clock stop instruction the clock stop instruction, stop s, is effective only when the ce pin is at a low level. if the stop s instruction is executed when the ce pin is at a high level, it is treated as a no-operation (nop) instruction. 13.3.2 resetting the device driving the ce pin from a low to a high can reset the device (ce reset). there is another type of reset, which is a power-on reset. it occurs when supply voltage v dd is turned on. see chapter 14 for details. 13.3.3 signal inputs to the ce pin the ce pin does not accept a high or low level with a duration of less than 187.5 m s to prevent malfunction due to noise. the input level of a signal supplied to the ce pin is checked using the ce flag in the control register (bit b 0 at address 07h). fig. 13-2 shows the relationship between the input signal and ce flag. fig. 13-2 relationship between the input signal and ce flag ce pin ce flag less than 187.5 s less than 187.5 s ce reset stop instruction disabled (nop) stop instruction enabled stop instruction disabled (nop); a ce reset occurs next time the timer carry ff is set. 187.5 s 187.5 s mm m m
156 m pd17062 13.4 halt function the halt function stops the operation of the cpu clock by executing the halt h instruction. when the halt h instruction is executed, the program stops at this instruction and rests there until the halt state is released. in the halt state, the current drain in the device is reduced by the amount required by the cpu to operate. the halt state can be released using the timer carry ff, interrupt, and key entry. the operand h of the halt h instruction specifies a condition (timer carry ff, interrupt, or key entry) to release the halt state. the halt h instruction is always effective regardless of the input level at the ce pin. sections 13.4.1 to 13.4.5 explain the halt state and halt release conditions. 13.4.1 halt state the cpu is entirely at a stop in the halt state. in the halt state, the program completely stops at the halt h instruction. in the halt state, however, the peripheral hardware continues operating as it did before execution of the halt h instruction.
157 m pd17062 13.4.2 halt release conditions fig. 13-3 summarizes the release conditions. as shown in fig. 13-3, the halt release condition is 4-bit data specified in the operand h of the halt h instruction. the halt state is released when a condition specified as 1 in the operand h is satisfied. upon release of the halt state, the subsequent instructions after the halt h instruction are executed sequentially. if multiple release conditions are specified at a time, the halt state is released when only one of them is satisfied. also when a power-on or ce reset occurs, the halt state is released and the device is reset. if the operand h is 0000b, no halt release condition is specified. under this condition, the halt state is released by resetting (power-on or ce reset) the device. sections 13.4.3 to 13.4.6 explain the timer carry ff, interrupt, and key entry as halt release conditions. fig. 13-3 halt release conditions b 3 b 2 b 1 b 0 0 1 halt h (4 bits) operand bits specify a condition to release the halt state. the halt state is released by a high level applied to a key entry pin (p0d 3 /adc 5 to p0d 0 /adc 2 pins). the halt state is released when the timer carry ff is set to 1. undefined (to be fixed at 0) the halt state is released when an interrupt (int nc pin, timer, v sync , serial interface) is accepted. the halt state is not released even when the condition is satisfied. the halt state is released when the condition is satisfied.
158 m pd17062 13.4.3 halt release by key entry the halt 0001b instruction specifies a key entry as a halt release condition. if this condition is specified, the halt state is released when a high level is applied to one of the p0d 0 /adc 2 to p0d 3 /adc 5 pins. items (1) to (3) describe cautions to be taken in using a general-purpose output port as a key source signal and the p0d 0 /adc 2 to p0d 3 /adc 5 pins for an a/d converter. (1) cautions in using a general-purpose output port as a key source signal p0d 3 /adc 5 p0d 2 /adc 4 p0d 1 /adc 3 p0d 0 /adc 2 latch switch a general-purpose output port the halt 0001b instruction must be executed after the general-purpose output port for key source signal input is raised to a high. if an alternate switch, like switch a in the above figure, is used, a high level is always applied to the p0d 0 / adc 2 pin when the switch is kept closed, and causes the halt state to be released immediately. therefore, great care should be taken when an alternate switch is used. the p0d 0 /adc 2 to p0d 3 /adc 5 pins are internally pulled down automatically.
159 m pd17062 (2) cautions in using the p0d 0 /adc 2 to p0d 3 /adc 5 pins for an a/d converter p0d 3 /adc 5 p0d 2 /adc 4 p0d 1 /adc 3 p0d 0 /adc 2 a/d input a/d input latch general-purpose port if one of the p0d 0 /adc 2 to p0d 3 /adc 5 pins is selected for an a/d converter (only one pin can be selected at one time), it is disconnected from the input latch and connected to the internal a/d converter input. if a pin happens to be at a high level when it is selected for an a/d converter, the latch circuit is held at a high. if the halt 0001b instruction is executed under the above condition, the halt state is released immediately because the input latch is at a high. to solve the above problem, specify the input port so that a low level is input to the a/d converter, before executing the halt 0001b instruction.
160 m pd17062 (3) alternative method to release the halt state p0d 3 /adc 5 p0d 2 /adc 4 p0d 1 /adc 3 p0d 0 /adc 2 output port latch microprocessor or the like general-purpose output port the p0d 0 /adc 2 to p0d 3 /adc 5 pins can be used a general-purpose input port with a built-in pull-down resistor. this configuration of the p0d 0 /adc 2 to p0d 3 /adc 5 pins enables a microprocessor to be used to release the halt state as shown above.
161 m pd17062 13.4.4 releasing the halt state by the timer carry ff the halt 0010b instruction specifies the timer carry ff as a halt release condition. if it is specified that the halt state is to be released according to the timer carry ff, the halt state is released immediately when the timer carry ff is set to 1. the timer carry ff corresponds to the btm0cy flag (bit b 0 at address 17h) in the control register on a one- to-one basis, and is set to 1 at constant intervals (5 or 100 ms). use of the timer carry ff can therefore release the halt state at constant intervals. an example of using the halt 0010b instruction follows: example hlttmr dat 0010b ; defines a symbol. initflg not btm0zx, not btm0ck2, not btm0ck1, not btm0ck0 ; built-in macro ; specifies the timer carry ff setting time interval as 100 ms. loop1: mov m1, #0110b loop2: halt hlttmr ; specifies the timer carry ff as a halt release condition. skt1 btm0cy ; built-in macro br loop ; branches to loop2 if the btm0cy flag is not set. add m1, #0001b ; adds 0001b to the contents of m1. skt1 cy ; built-in macro br loop2 ; performs process a if there is a carry. process a br loop1 this sample program releases the halt state at intervals of 100 ms and perform process a at intervals of 1 s.
162 m pd17062 13.4.5 releasing the halt state by an interrupt the halt 1000b instruction specifies an interrupt as halt release condition. if it is specified that the halt state is to be released according to an interrupt, the halt state is released immediately when an interrupt request is accepted. four interrupt sources, int nc pin, timer, v sync , and serial interface, can be used as a condition to release the halt state. it is necessary to program which interrupt source is to be used as a halt release condition, beforehand. for an interrupt request to be accepted, besides issuing the interrupt request, it is necessary to enable all interrupts (ei instruction) and the interrupt that corresponds to the issued interrupt request (to set the interrupt permission flag). if interrupts are not enabled, no interrupt request is accepted and therefore the halt state is not released, even if an interrupt request is issued. if an interrupt request is accepted and the halt state is released, program control is passed to the vector address of the corresponding interrupt. after the required interrupt handling is finished, when the ret1 instruction is executed, program control is returned to the instruction just after the halt instruction. this is explained in the following example.
163 m pd17062 example hltint dat 1000b ; defines a symbol. start: ; address 0000h br main ; nop inttm: ; timer interrupt vector address (0003h) br inttimer ; branches to inttimer (interrupt handling). int0: ; int nc pin interrupt vector address (0004h) process a ; interrupt requested at the int nc pin ei reti inttimer: process b ; timer interrupt handling ei reti main: set2 ipbtm0, ipnc ; built-in macro ; enables int nc pin and timer interrupts. set1 btm0ck2 ; built-in macro loop: ; specifies the timer interrupt time interval as 5 ms. process c ; main routine processing ei ; enables all interrupts. halt hltint ; specifies an interrupt as a halt release condition. ; # br loop this sample program releases the halt state and performs process b when a timer interrupt request is accepted. when an interrupt request at the int nc pin is issued, the program performs process a. it also performs process c each time the halt state is released. if an int nc pin interrupt is requested exactly at the same time with a timer interrupt during the halt state, the program performs process a for the int nc pin interrupt, which has a higher hardware priority than the timer interrupt. when a reti instruction is executed upon completion of process a, program control is returned to the br loop instruction at # , but this instruction will not be executed. instead, the timer interrupt request is accepted immediately. the br loop instruction is executed only after a reti is executed upon completion of process b (timer interrupt handling).
164 m pd17062 13.5 clock stop function the clock stop function stops the operation of the 8 mhz crystal oscillator by executing the stop s instruction. the clock stop function can reduce the current drain of the m pd17062 by 10 m a (maximum). the operand s of the stop s instruction is 0000b. this instruction is effective only when the ce pin is at a low level. if executed when the ce pin is at a high, the stop s instruction is regarded as a no-operation instruction (nop). in other words, the stop s instruction should be executed when the ce pin is at a low. a ce reset is used to release the clock stop state. sections 13.5.1 to 13.5.3 describe the clock stop state, how to release the clock stop state, and cautions to be taken in using the clock stop instruction. 13.5.1 clock stop state in the clock stop state, all operations of the device, including cpu and peripheral hardware operations, are stopped, because the crystal oscillator stops. during the clock stop state, the power-failure detector does not operate even if the supply voltage v dd is lowered to about 2.2 v. this makes possible a low-voltage data memory backup. 13.5.2 releasing the clock stop state the clock stop state is released by raising the level of the ce pin from a low to a high (ce reset) or by lowering the supply voltage v dd of the device below 2.2 v, then increasing it to 4.5 v (power-on reset). figs. 13-4 and 13-5 show how the clock stop state is released by a ce reset and power-on reset, respectively. releasing the clock stop state using a power-on reset causes the power-failure detector to start operating.
165 m pd17062 fig. 13-4 releasing the clock stop state by a ce reset fig. 13-5 releasing the clock stop state by a power-on reset 5 v 0 v v dd ce pin crystal oscillation (x out pin) stop 0 instruction approx. 50 ms program starts at address 0 (ce reset) 5 v 0 v v dd ce pin clock oscillation (x out pin) if a clock-stop instruction is not used, operation is as follows: 0-t set program starts at address 0 (ce reset) ce reset is applied in synchronization with the setting of the timer carry ff after the ce pin has been raised to high level. 5 v 0 v v dd ce pin crystal oscillation (x out pin) stop 0 instruction approx. 50 ms program starts at address 0 (ce reset) 5 v 0 v v dd ce pin clock oscillation (x out pin) if a clock-stop instruction is not used, operation is as follows: approx. 50 ms program starts at address 0 (ce reset) oscillation stopped 3.5 v 2.2 v
166 m pd17062 13.5.3 cautions in using the clock stop instruction the clock stop instruction (stop s) is effective only when the ce pin is at a low level. to enable the clock stop state to be released, the program must therefore have a provision to handle when the ce pin happens to be at a high. such a provision is explained using the example below. example xtal dat 0000b ; defines a symbol for the clock stop condition. cejdg: ; # skf1 ce ; built-in macro ; checks the input level at the ce pin. br main ; branches to the main process if the ce pin is high. process a ; processing performed when the ce pin is low ; $ stop xtal ; stops the clock. ; % br $ - 1 main: main process br cejdg the above program checks the ce pin at # . if the ce pin is at a low, the clock stop instruction (stop xtal) at $ is executed after process a is finished. if the ce pin goes high during execution of the stop xtal instruction at $ as shown below, the stop xtal instruction is treated as a no-operation (nop). if the program does not contain the branch instruction (br $ - 1) at % , program control is passed to the main process, possibly resulting in a malfunction. the program must always have a branch instruction at % or have a provision that can prevent a malfunction in the main process. even if the ce pin remains high, the branch instruction at $ allows a ce reset to occur next time the timer carry ff is set. 5 v 0 v v dd ce pin ## # $ stop xtal the stop xtal becomes a nop instruction because the ce pin is high level. the program starts from address 0 in synchronization with setting of the timer carry ff. (ce reset) main proces- sing process a ce pin detection
167 m pd17062 13.6 operation of the device at a halt or clock stop 13.6.1 state of each pin at a halt and clock stop table 13-1 summarizes how the cpu and peripheral hardware behave during the halt or clock stop state. during the halt state, execution of the cpu instructions is suspended, but the peripheral hardware operates normally, as described in table 13-1. during the clock stop state, on the other hand, all peripheral hardware is at a stop. during the halt state, the control register that controls the operating state of the peripheral hardware works as usual (not initialized). during the clock stop state (when the stop s instruction is executed), on the other hand, the control register is initialized to a specified value. to put in another way, the peripheral hardware keeps operating as specified in the control register during the halt state. during the clock stop state, however, the peripheral hardware operates according to the initial value set in the control register. see chapter 9 for the initial value for the control register. lets study the following example. example when the p0a 0 /sda and p0a 1 /scl pins of port 0a are specified as output ports, and the p0a 2 / sck and p0a 3 /so pins are used as a serial interface hltint dat 1000b ; defines a symbol. xtal dat 0000b ; initflg p0abio3, p0abio2, p0abio1, p0abio0 ; built-in macro ; # set2 p0a0, p0a1 ; initflg sio0ch, not sb, sio0ms, sio0tx ; set2 sio0ck1, sio0ck0 ; $ set2 sio0imd1, sio0imd0 clr1 irqsio0 set1 ipsio0 ei ; % set1 sio0nwt ; & halt hltint ; ( stop xtal the above program outputs a high level from the p0a 0 and p0a 1 pins at # , specifies a serial interface condition at $ , and starts serial communication at % . when the halt instruction is executed at & , the serial communication continues, and the halt state is released after a serial interface interrupt request is accepted.
168 m pd17062 stops at the address of the halt instruction. holds the previous state. holds the previous state. holds the previous state. operates normally. operates normally. operates normally. stops operating. operates normally. operates normally. operates normally. holds the same state as when the halt instruction is executed. if the stop instruction at ( is executed in place of the halt instruction at & , all flags in the control register set up at # , $ , and % are initialized, and therefore, the serial communication is suspended and all pins of port 0a are specified as general-purpose input/output ports. table 13-1 behavior of the device at the halt and clock stop states peripheral hardware state ce pin = low level halt clock stop clock stop halt ce pin = high level program counter system register peripheral hardware register control register timer a/d converter d/a converter serial interface general-purpose input/output port general-purpose input port general-purpose output port idc initialized to 0000h and stops. initializednote. holds the previous state. initializednote. stops operating. stops operating. stops operating. stops operating. works as input port. works as input port. holds the previous state. stops operating. note see chapters 8 and 9 for the initial values. the stop instruction is invalid (nop). stops at the address of the halt instruction. holds the previous state. holds the previous state. holds the previous state. operates normally. operates normally. operates normally. stops operating. operates normally. operates normally. operates normally. stops operating.
169 m pd17062 13.6.2 cautions in processing of each pin during halt or clock stop state the halt function is intended to reduce the required current drain, for example, by allowing only the clock to operate. meanwhile, the clock stop function is intended to reduce the required current drain by suspending all operations except preservation of data in memory. during the halt or clock stop state, therefore, it is necessary to reduce the required current drain as much as possible. because the current drain varies with the state of each pin, it is necessary to take cautions listed in table 13-2. table 13-2 state of each pin during the halt or clock stop state and cautions to be taken (1/2) these pins are specified as general- purpose input ports. all input ports except the p0a 1 /scl and p0a 0 /sda pins are designed so that even if they are floating externally, the current drain will not increase due to noise. for the p0a 1 /scl and p0a 0 / sda pins, an external pull-down resistor or pull-up resistor must be connected to keep the current drain from increasing. port 0d (p0d 3 /adc 5 to p0d 0 /adc 2 ) are pulled down internally. these pins are specified as general- purpose ports. the outputs are preserved. therefore, if they are pulled down externally during high-level output or pulled up during low-level output, the current drain will increase. the state that exists before the execution of the halt instruction continues. (1) when the port is specified as output if the pin pulled down externally during high-level output or pulled up externally during low-level output, the current drain increases. be careful especially for n-channel open-drain outputs (p0a 1 , p0a 0 , p1a 3 to p1a 0 ). (2) when the port is specified as input when the pin is floating, the current drain increases due to noise. (3) port 0d (p0d 3 /adc 7 to p0d 0 /adc 4 ) because the pin is already pulled down internally, the current drain will increase if it is pulled up externally. if the pin is selected for a/d converter, however, the internal pull-down resistor is disconnected. (4) port0b (p0b 3 /hscnt to p0b 0 /si) and port1b (p1b 3 /p1b 0 ) when the p0b 3 /hscnt pin operates as the hsync counter or when the p1b 3 pin operates as an external timer input, the built-in self-bias circuit operates, resulting in an increase in the current drain. p0a 3 /so p0a 2 /sck p0a 1 /scl p0a 0 /sda p0b 3 /hscnt p0b 2 /tmin p0b 1 p0b 0 /si p1b 3 p1b 2 p1b 1 p1b 0 p1c 3 /adc 1 p1c 2 p1c 1 p0d 3 /adc 5 p0d 2 /adc 4 p0d 1 /adc 3 p0d 0 /adc 2 p0c 3 p0c 2 p0c 1 p0c 0 general-purpose output port general-purpose input port general-purpose input/output port port0a port0b port1b port1c port0d port0c clock stop state state of each pin and cautions in processing halt state pin symbol pin function
170 m pd17062 table 13-2 state of each pin during the halt or clock stop state and cautions to be taken (2/2) int nc red green blue blank h sync v sync pwm 3 pwm 2 pwm 1 pwm 0 adc 0 x in x out clock stop state state of each pin and cautions in processing halt state pin symbol pin function if the pin is floating, external noise causes the current drain to increase. the output pins remain in the state in which they were when the halt instruction was executed. if the idcen flag is set, the current drain increases. it is necessary to take the same cautions as for the general-purpose output port. the pin becomes floating. the current drain varies with the waveform of the oscillation output of the clock oscillator. the larger the amplitude, the current drain becomes lower. the oscillation amplitude of the oscillator varies depending on its crystal and load capacitance; evaluation is required. the idc is disabled. each pin behaves as follows: the current drain will not increase, even if the red, green, and blue pins output a low level, or the h sync and v sync pins are floating. all pins output a low level. the x in pin is internally pulled down, and the x out pin outputs a high level. interrupt idc d/a converter a/d converter clock oscillator
171 m pd17062 14. reset the reset function is used to initialize device operation. 14.1 reset block configuration fig. 14-1 shows the configuration of the reset block. device reset is divided into reset by turning on v dd (power-on reset or v dd reset), and reset by ce pin (ce reset). the power-on reset block consists of a voltage detection circuit that detects the voltage applied to the v dd pin, a power failure detection circuit, and a reset control circuit. the ce reset block consists of a circuit that detects the rising edge of the signal input to the ce pin, and a reset control circuit. fig. 14-1 reset block x out x in v dd ce power-on clear signal (poc) reset signal ires res reset stop instruction r s q selector timer carry ff timer ff block power failure detection block scaler btm0cy flag read stop instruction voltage detection circuit control register system register stack program counter forced halt by timer carry ff rising edge detection circuit timer carry disable ff reset control circuit
172 m pd17062 14.2 reset function power-on reset is applied when v dd rises from a certain voltage, ce reset is applied when the ce pin rises from low level to high level. power-on reset initializes the program counter, stack, system register and control registers, and executes the program from address 0000h. ce reset initializes the program counter, stack, system register and some control registers, and executes the program from address 0000h. the main differences between power-on reset and ce reset are the operation of the control registers that are initialized and the power failure detection circuit described in section 14.6 . power-on reset and ce reset are controlled by reset signals ires, res, and reset output from the reset control circuit in fig. 14-1. table 14-1 shows the ires, res, and reset signal and power-on reset and ce reset relationship. the reset control circuit also operates when the clock-stop instruction (stop) described in chapter 13 is executed. sections 14.3 and 14.4 describe ce reset and power-on reset, respectively. section 14.5 describes the relationship between ce reset and power-on reset. table 14-1 relationship between internal reset signal and each reset output signal internal reset signal at ce reset at power- at clock-stop contents controlled by each reset signal on reset ires l l l l forces the device into the halt state. the halt state is released by the setting of the timer carry ff. res l l l l initializes some control registers. reset l l l l l l initializes the program counter, stack, system register, and some control registers.
173 m pd17062 14.3 ce reset ce reset is executed by raising the ce pin from low level to high level. when the ce pin rises to high level, the reset signal is output and the device is reset in synchronization with the rising edge of the pulse used for the next setting of the timer carry ff. when ce reset is applied, the reset signal initializes the program counter, stack, system register, and some control registers to their initial value and executes the program from address 0000h. for the initial values, see the relevant item. ce reset operation is different when clock-stop is used and when it is not used. these operations are described in sections 14.3.1 and 14.3.2 , respectively. section 14.3.3 describes the cautions at ce reset. 14.3.1 ce reset when clock-stop (stop instruction) not used fig. 14-2 shows the reset operation. when clock-stop (stop instruction) is not used, the timer mode selection register of the control registers is not initialized. therefore, after the ce pin becomes high level, the reset signal is output, and reset is applied at the rising edge of the timer carry ff set pulse (5 or 100 ms) . fig. 14-2 ce reset operation when clock-stop not used 5 v 0 v normal operation normal operation x out v dd ce timer carry ff set pulse ires res reset reset signal ce reset is applied at the rising edge of the timer carry ff set pulse. this period, t, varies with the timing when the ce pin signal rises. it falls in the range from 0 to t set (0 < t < t set ), which is the selected set time of the timer carry ff . the program continues to run during this period. "h" "h"
174 m pd17062 14.3.2 ce reset when clock-stop (stop instruction) used fig. 14-3 shows the reset operation. when clock-stop is used, the ires, res and reset signals are output at the time the stop instruction is executed. at this time, the res signal initializes the timer mode selection register of the control registers to 0000b and sets the timer carry ff set signal to 100 ms. since the ires signal is output continuously while the ce pin is low level, release by timer carry ff is forcibly halted. since the clock itself stops, the device stops operating. when the ce pin rises to high level, the clock-stop state is released and oscillation begins. the ires signal halts release by timer carry ff. when the timer carry ff set pulse rises after the ce pin rises, the halt state is released and the program starts from address 0. since the timer carry ff set pulse is initialized to 100 ms, ce reset is applied 50 ms after the ce pin rises to high level. fig. 14-3 ce reset operation when clock-stop used 5 v 0 v normal operation clock-stop state x out v dd ce timer carry ff set pulse ires res reset reset signal ce reset program starts from address 0. clock stop release oscillation start stop 0000b halt state 50 ms
175 m pd17062 14.3.3 cautions at ce reset when ce reset is used, careful attention must be given to points (1) and (2) below regardless of the instruction being executed. (1) time required for clock and other timer processing when writing a clock program by using timer carry ff and timer interrupts, the program must end processing within a certain time. for details, see sections 12.4 and 12.6. (2) processing of data, flags, etc. used in the program care must be exercised when rewriting the contents of data, flags, etc. that cannot be processed by one instruction so that the contents, such as the last channel, do not change even when ce reset is applied. two examples are given below: example 1. ; # lctune : initial reception ; the last channel is received. the channel indicated by the contents of m1 and m2 is received. main : ; main processing channel change ; the changed channel is assigned to general-purpose ; registers r1 and r2. ; $ st m1, r1 ; the last channel is rewritten. ; % st m2, r2 br main in this example, if the last channel is 12h, then the data memory contents of m1 and m2 will be 1h and 2h, respectively. when ce reset is applied, the last channel (channel 12) is received in # . when the channel is changed in the main processing, the changed channel is rewritten to m1 and m2 in $ and % . when the channel is changed to 04h, 0h and 4h are rewritten to m1 and m2 in $ and % . if ce reset is applied after $ , the reset process runs without executing % . since this results in the last channel being 02h, channel 02 is received in # . this can be avoided by using a program shown in example 2.
176 m pd17062 example 2. ; & skt1 flg1 ; if flg1 is set to 1, br lctune st m1, r1 ; data is rewritten to m1 and m2 again. st m2, r2 clr1 flg1 ; # lctune : initial reception ; the last channel is received. the channel indicated by the contents of m1 and m2 is received. main : ; main processing channel change ; the changed channel is assigned to general-purpose ; registers r1 and r2. ; ( set1 flg1 ; flg1 is set while rewriting the last channel. ; $ st m1, r1 ; the channel is rewritten. ; % st m2, r2 clr1 flg1 br main in this example, flg1 is set when rewriting the last channel in $ and % . this allows data to be rewritten in & again even if ce reset is applied in % .
177 m pd17062 14.4 power-on reset power-on reset is executed by raising v dd from a certain voltage (called the power-on clear voltage) or less. when v dd is less than the power-on clear voltage, the power-on clear signal (poc) is output from the voltage detection circuit shown in fig. 14-1. when the power-on clear signal is output, the crystal oscillation circuit stops and the device stops operating. while the power-on clear signal is being output, the ires, res and reset signals are output. when v dd exceeds the power-on clear voltage, the power-on clear signal is dropped and crystal oscillation starts. at the same time, the ires, res and reset signals are also dropped. since the ires signal halts release by timer carry ff, power-on reset is applied at the rising edge of the next timer carry ff set signal. since the reset signal has initialized the timer carry ff set signal to 100 ms, 50 ms after v dd exceeds the power-on clear voltage, reset is applied and the program starts from address 0. this operation is shown in fig. 14-4. at power-on reset, the program counter, stack, system register and control registers are initialized when the power-on clear signal is output. for the initial values, see the relevant items. during normal operation, the power-on clear voltage is 3.5 v (rated value). in the clock-stop state, the power-on clear voltage becomes 2.2 v (rated value). sections 14.4.1 and 14.4.2 describe operation at this time. section 14.4.3 describes operation when v dd rises from 0 v, fig. 14-4 power-on reset operation 5 v 0 v ? normal operation device operation stopped x out v dd ce timer carry ff set pulse ires res reset reset signal power-on reset program starts from address 0 power-on clear signal power-on clear release oscillation start halt state 50 ms power-on clear voltage
178 m pd17062 14.4.1 power-on reset at normal operation fig. 14-5 (a) shows power-on reset at normal operation. as shown in fig. 14-5 (a), when the v dd drops below 3.5 v, the power-on clear signal is output and operation of the device stops regardless of the input level of the ce pin. when v dd then rises to 3.5 v or greater, after a 50 ms halt, the program starts from address 0000h. normal operation refers to the state in which the clock-stop instruction is not used. this also includes the halt state set by the halt instruction. 14.4.2 power-on reset in clock-stop state fig. 14-5 (b) shows power-on reset in the clock-stop state. as shown in fig. 14-5 (b), when v dd drops below 2.2 v, the power-on clear signal is output and device operation stops. however, since the device is in the clock-stop state, its operation apparently does not change. when v dd rises to 3.5 v or greater, after a 50 ms halt, the program starts from address 0000h. 14.4.3 power-on reset when v dd rises from 0 v fig. 14-5 (c) shows power-on reset when v dd rises from 0 v. as shown in fig. 14-5 (c), the power-on clear signal is being output while v dd is rising from 0 to 3.5 v. when v dd rises above the power-on clear voltage, the crystal oscillation circuit starts and after a 50 ms halt, the program starts from address 0000h.
179 m pd17062 fig. 14-5 power-on reset and v dd (a) during normal operation (including halt state) (b) at clock-stop (c) when v dd rises from 0 v 5 v 0 v ? normal operation device operation stopped x out v dd ce power-on clear signal power-on clear release oscillation start power-on reset program starts from address 0 halt state 50 ms power-on clear voltage 3.5 v 5 v clock-stop device operation stopped x out v dd ce power-on clear signal power-on clear release oscillation start power-on reset program starts from address 0 halt state 50 ms 2.2 v power-on clear voltage 3.5 v stop 0000b normal operation ? 5 v 0 v device operation stopped x out v dd ce power-on clear signal power-on clear release oscillation start power-on reset program starts from address 0 halt state 50 ms 3.5 v power-on clear voltage ?
180 m pd17062 14.5 relationship between ce reset and power-on reset when supply voltage is first turned on, power-on reset and ce reset may be applied simultaneously. sections 14.5.1 through 14.5.3 describe this reset operation. section 14.5.4 describes the cautions when supply voltage rises. 14.5.1 when v dd pin and ce pin rise simultaneously fig. 14-6 (a) shows the reset operation. power-on reset starts the program from address 0000h. 14.5.2 when ce pin raised in forced halt state caused by power-on reset. fig. 14-6 (b) shows the reset operation. power-on reset starts the program from address 0000h, as in section 14.5.1. 14.5.3 when ce pin raised after power-on reset fig. 14-6 (c) shows the reset operation. power-on reset starts the program from address 0000h. ce reset restarts the program from address 0000h at the rising edge of the next timer carry ff set signal.
181 m pd17062 fig. 14-6 relationship between power-on reset and ce reset (a) when v dd and ce pin raised simultaneously (b) when ce pin raised in halt state (c) when ce pin raised after power-on reset 5 v 0 v opera- tion stopped v dd ce power-on reset program start power-on clear voltage 3.5 v halt state 50ms normal operation timer carry ff set pulse 5 v 0 v v dd ce power-on reset program start power-on clear voltage 3.5 v halt state 50 ms normal operation timer carry ff set pulse opera- tion stopped 0 v v dd ce timer carry ff set pulse power-on reset program start power-on clear voltage 3.5 v halt state 50 ms normal operation ce reset program start opera- tion stopped 5 v
182 m pd17062 14.5.4 cautions when supply voltage raised when supply voltage is raised, careful attention must be given to points (1) and (2) below. (1) when v dd raised from power-on clear voltage when v dd is raised, it must be raised to 3.5 v or greater, once. this is shown in fig. 14-7. as shown in fig. 14-7, when a voltage under 3.5 v is applied when v dd is turned on in a program that uses clock-stop to back up v dd at 2.2 v, for example, the power-on clear signal continues to be output and the program does not run. since the device output port outputs an undefined value, the supply current increases, according to the situation, reducing the back-up time with a battery considerably. fig. 14-7 caution when v dd raised 5 v 0 v operation stopped x out v dd ce power-on clear signal timer carry ff set pulse 3.5 v 2.2 v opera- tion stopped halt state 50 ms normal operation back-up since the values of the output ports, etc. are undefined during this period, the current drain may increase. during this period, initialization is per- formed, then the clock is stopped. power-on reset program start stop 0000b power-on clear voltage
183 m pd17062 (2) at return from clock-stop state when returning from the back-up state when clock-stop is used to back-up supply voltage at 2.2 v, v dd must be raised to 3.5 v or greater within 50 ms after the ce pin becomes high level. as shown in fig. 14-8, return from the clock-stop state is performed by ce reset. since the power-on clear voltage is switched to 3.5 v 50 ms after the ce pin is raised, if v dd is not 3.5 v or greater at this time, power- on reset is applied. the same caution is necessary when v dd is dropped. fig. 14-8 return from clock-stop state 5 v 0 v x out v dd ce power-on clear signal timer carry ff set pulse 3.5 v 2.2 v ce = low processing normal operation back-up back-up caused by clock stop power-on clear voltage halt state 50 ms ce reset program start stop 0000b at this point, the power-on clear voltage is switched to 2.2 v. therefore, v dd must not be dropped below 2.2 v before this point. at this point, the power-on clear voltage is switched to 3.5 v. therefore, v dd must be raised to 3.5 v or greater before this point.
184 m pd17062 14.6 power failure detection power failure detection is used to judge whether the device is reset by turning on v dd or by the ce pin, as shown in fig. 14-9. since the contents of the data memory, output ports, etc. become undefined when v dd is turned on, they are initialized by power failure detection. fig. 14-9 power failure detection flowchart 14.6.1 power failure detection circuit as shown in fig. 14-1, the power failure detection circuit consists of a voltage detection circuit and timer carry disable ff that is reset by the output (power-on clear signal) of the voltage detection circuit, and timer carry ff. the timer carry disable ff is set to 1 by the power-on clear signal and is reset to 0 when a btm0cy flag (address 17h, bit b 0 ) read instruction is executed. when the timer carry disable ff is set to 1, the btm0cy flag is not set to 1. that is, when the power-on clear signal is output (at power-on reset), the program starts in the state in which the btm0cy flag is reset and the setting disabled state is set until a btm0cy read instruction is executed thereafter. once a btm0cy read instruction is executed, the btm0cy flag is set at each rising edge of the timer carry ff set pulse thereafter. when reset is applied to the device, the contents of the btm0cy flag are monitored. if the btm0cy flag has been reset to 0, power-on reset (power failure) is judged and if the btm0cy flag has been set to 1, ce reset (no power failure) is judged. since the voltage that can detect a power failure is the same as the voltage applied by power-on reset, v dd becomes 3.5 v at clock oscillation and 2.2 v at clock-stop. fig. 14-10 shows the btm0cy flag state transition. fig. 14-11 shows timing chart and btm0cy flag operation specified in fig. 14-10. program start power failure no power failure data memory, output port, etc. initialization power failure detect- ion
185 m pd17062 fig. 14-10 btm0cy flag state transition # $ v dd = l ? 3.5 v ce = l ce = h ( &)* + , -. 0 /12 3 4 ce = h ? l stop 0 btm0cy = 0 ce = l ? h ce = l ? h ce = h ? l ce = l ? h ce = l ? h stop 0 btm0cy = 1 ce = low ce = optional ce = high v dd = low operation stopped clock oscillation start forced halt (approx. 50 ms) power-on reset normal operation ce reset rising edge of timer carry ff set pulse clock-stop btm0cy flag setting disabled state normal operation normal operation ce reset wait clock oscillation start forced halt (50 ms) skt1 btm0cy or skf1 btm0cy skt1 btm0cy or skf1 btm0cy normal operation ce reset rising edge of timer carry ff set pulse clock-stop normal operation normal operation ce reset wait clock oscillation start forced halt (50 ms) btm0cy flag setting enable state %
186 m pd17062 fig. 14-11 btm0cy flag operation (a) when btm0cy flag not detected even once (neither skt1 btm0cy nor skf1 btm0cy executed) (b) when power failure detected with btm0cy flag 5 v 0 v v dd ce timer carry ff set pulse btm0cy fig. 14-12 operation timer time switching stop 0000b #$ ) ( + ) ( & , ) # * * % 5 v 0 v v dd ce timer carry ff set pulse btm0cy skt1 btm0cy instruction timer time switching stop # % fig. 14-12 operation $)1 0 3 1 0 / 4 1 # btm0cy = 0 power failure btm0cy = 1 no power failure btm0cy = 1 no power failure 2 2 .
187 m pd17062 14.6.2 cautions at power failure detection with btm0cy flag when clock counting, etc. is performed with the btm0cy flag, careful attention must be given to the following points. (1) clock updating when writing a clock program by using the timer carry ff, the clock must be updated after a power failure. this is because the btm0cy flag is reset to 0 and one clock count is lost by btm0cy flag reading when a power failure is detected. (2) clock update processing time when the clock is updated, its processing must end before the next rising edge of the timer carry ff set pulse. this is because if the ce pin rises to high level during clock update processing, the clock update processing will not be executed up to the end and a ce reset will be applied. for (1) and (2) above, see section 12.4.2. when processing is performed at a power failure, careful attention must be given to the following point. (3) power failure detection timing when clock counting, etc. is performed with the btm0cy flag, the flag must be read for power-failure detection before the next rising edge of the timer carry ff set pulse, after a program starts from address 0000h. this is because when the timer carry ff set time is set to 5 ms, for instance, and power failure detection is performed 6 ms after the program starts, one btm0cy flag is lost. see section 12.4.2. as shown in the example on the next page, power failure detection and initialization must be performed within the timer carry ff set time. this is because when the ce pin is raised and ce reset is applied during power failure processing and initialization, these processings are interrupted and a problem may occur. when the timer carry ff set time is changed in initialization, an instruction that makes the change must be executed at the end of initialization. this is also because when the timer carry ff set time is switched before initialization as shown in the example on the next page, initialization by ce reset may not be executed up to the end.
188 m pd17062 example sample program start: ; program address 0000h ; # reset processing ; ; $ skt1 btm0cy ; power failure detection br initial backup: ; % clock updating br main initial: ; & initialization ; ( initflg not btm0zx, not btm0ck2, not btm0ck1, btm0ck0 ; built-in macro ; sets timer carry ff set time to 5 ms. main: skt1 btm0cy br main clock updating operation example 5 v 0 v v dd ce timer carry ff set pulse # 50 ms 50 ms $ power failure detection &#% $ power failure detection ce reset ce reset when the processing time of # + % is too long, a ce reset is applied. when the processing time of # + & is 100 ms or longer, a ce reset is applied midway through processing & . ( ce reset may be applied immediately, depending on the timer carry ff set time switching timing. when ( is executed before & , power failure processing & may not be executed.
189 m pd17062 15. general-purpose port a general-purpose port outputs a high level, low level, or floating signal to an external circuit and reads a high level or low level signal from an external circuit. 15.1 configuration and classification of general-purpose port fig. 15-1 shows a block diagram of the general-purpose port. table 15-1 lists the classifications of general-purpose ports. as shown in fig. 15-1, the general-purpose port consists of port0a (p0a) to port1c (p1c), that set data according to addresses 70h to 73h (port register) in each bank of data memory. the same port register is mapped to both bank0 and bank2. each port consists of general-purpose port pins. for example, port0a consists of pin p0a 3 to pin p0a 0 . as stated in table 15-1, general-purpose ports are classified into i/o shared ports (i/o ports), input-only ports (input ports), and output-only ports (output ports). i/o ports are classified into bit i/o ports which allow i/o to be specified in 1-bit (1-pin) units and group i/o ports in which i/o can be specified in 3-bit (3-pin) units . fig. 15-1 block diagram of general-purpose port p 0 a p 0 b p 0 c p 0 d p 1 a p 1 b p 1 c fixed at 0 p 0 a p 0 b p 0 c p 0 d p 0 a pin p 0 a pin p 0 a pin p 0 a pin bank0 bank1 bank2 0123456789abcdef 0 1 2 3 4 5 6 7 column address row address data memory port register system register bit i/o bit i/o bit i/o group i/o bit i/o bit i/o out in out in out i/o setting example configuration of p0a pins control register 3210
190 m pd17062 table 15-1 classification of general-purpose ports general-purpose ports classification of general-purpose ports target ports data setting method i/o shared port bit i/o port0a port register port0b port1b group i/o port1c port register input-only port port0d port register output-only port port0c port register port1a
191 m pd17062 b 3 b 2 b 1 b 0 m n p p p p 3 2 1 0 weight of port register bit port register address (examples: 70h = a, 71h = b, 72h = c, 73h = d) port register bank "p" of port port register bank address bit 15.2 functions of general-purpose ports a general-purpose i/o port, set up either as a general-purpose output port or output port, outputs high level or low level signals from each corresponding pin by setting data in the port register accordingly. a general-purpose i/o port, set up either as a general-purpose input port or input port, detects the level of the input signal applied to each corresponding pin by reading the contents of the port register. general-purpose i/o ports are set either as an input ports or output ports, according to the contents of the control register for each port. this enables i/o switching to be done by the program. since p0a to p0d and p1a to p1c are set as general-purpose ports at power-on reset, other pins that are used as peripheral hardware are set up independently according to the contents of the corresponding control register. sections 15.2.1 to 15.2.4 describe the functions of the port register and outline the functions of each port. 15.2.1 general-purpose port data register (port register) the port register sets output data for each general-purpose port and reads input data. since the port register is mapped into data memory, it can be manipulated by all data memory manipulation instructions. fig. 15-2 shows the relationship between the port register and each corresponding pin. output for each pin is set by setting data in the port register for the pin set as a general-purpose output port. the input state of each pin is detected by reading the contents of the port register for the pin set as a general- purpose output port. table 15-2 shows the relationship between each port (each pin) and the port register. fig. 15-2 relationship between port register and each pin reserved words are defined in the port register by the assembler. since reserved words are defined in flag units (bits), the assembler built-in macro instructions can be used. note that reserved words of data memory type are not defined in the port register.
192 m pd17062 15.2.2 general-purpose i/o ports (p0a, p0b, p1b, p1c) the i/o of p0a is switched by the p0a bit i/o selection register (rf address 37h). the i/o of p0b is switched by the p0b bit i/o selection register (rf address 36h). the i/o of p1b is switched by the p1b bit i/o selection register (rf address 35h). and, the i/o of p1c is switched by the p1c group i/o selection register (rf address 27h). the i/o data of p0a is set by p0a (data memory address: 70h of bank0 or bank2) of the port register. the i/o data of p0b is set by p0b (data memory address: 71h of bank0 or bank2) of the port register. the i/o data of p1b is set by p1b (data memory address: 71h of bank1) of the port register. and, the i/o data of p1c is set by p1c (data memory address: 72h of bank1) of the port register. see table 15-2. for details, see section 15.3 . 15.2.3 general-purpose input port (p0d) p0d input data is read by p0d (data memory address: 73h of bank0 or bank2) of the port register. see table 15-2. for details, see section 15.4 . 15.2.4 general-purpose output ports (p0c, p1a) (1) p0c, p1a p0c and p1a output data is set by p0c (data memory address: 72h of bank0 or bank2) and p1a (data memory address: 70h of bank1) of the port register. see table 15-2. for details, see section 15.5 .
193 m pd17062 table 15-2 relationship between each port (pin) and port register note nothing is mapped to b 0 of 72h. when b 0 is read, 0 is always read. port0a (p0a) port0b (p0b) port0c (p0c) port0d (p0d) port1a (p1a) port1b (p1b) port1c (p1c) p0a 3 p0a 2 p0a 1 p0a 0 p0b 3 p0b 2 p0b 1 p0b 0 p0c 3 p0c 2 p0c 1 p0c 0 p0d 3 p0d 2 p0d 1 p0d 0 p1a 3 p1a 2 p1a 1 p1a 0 p1b 3 p1b 2 p1b 1 p1b 0 p1c 3 p1c 2 p1c 1 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 p0a3 p0a2 p0a1 p0a0 p0b3 p0b2 p0b1 p0b0 p0c3 p0c2 p0c1 p0c0 p0d3 p0d2 p0d1 p0d0 p1a3 p1a2 p1a1 p1a0 p1b3 p1b2 p1b1 p1b0 p1c3 p1c2 p1c1 70h 71h 72h 73h 70h 71h 72h p0a p0b p0c p0d p1a p1b p1c bank0 bank2 bank1 port symbol i/o pin data setting method port register (data memory) bank address symbol bit symbol (reserved word) i/o (bit i/o) i/o (bit i/o) output input output i/o (bit i/o) i/o (group i/o) no target pins note
194 m pd17062 15.3 general-purpose i/o ports (p0a, p0b, p1b, p1c) 15.3.1 configuration of i/o ports in the following, (1) to (3) explain the configuration of the i/o ports. (1) p0a (p0a 3 , p0a 2 pins) p0b (p0b 3 , p0b 2 , p0b 1 , p0b 0 pins) p1b (p1b 3 , p1b 2 , p1b 1 , p1b 0 pins) p1c (p1c 3 , p1c 2 , p1c 1 pins) (2) p0a (p0a 1 , p0a 0 pins) 15.3.2 how to use i/o ports an i/o port is set as an input or output port according to the contents of each i/o selection register of p0a, p0b, p1b, and p1c of the control register. i/o of the bit i/o port (p0a, p0b, p1b) can be set in 1-bit (1-pin) units. i/o of the group i/o port (p0c) can be set in 3-bit (3-pin) units. output data is set and input data is read when a data write instruction or data read instruction is executed in the corresponding port register. section 15.3.3 describes the i/o selection register of each port. sections 15.3.4 and 15.3.5 explain the use of an input port and output port. v dd v dd or and 1 0 i/o switching flag output latch write instruction port register (1 bit) read instruction reset (except p1c) read instruction (p1c only) v dd and reset i/o switching flag output latch write instruction port register (1 bit) read instruction
195 m pd17062 15.3.3 port0a bit i/o selection register (p0abio) port0b bit i/o selection register (p0bbio) port1b bit i/o selection register (p1bbio) port1c group i/o selection register (p1cgpio) the port0a bit i/o selection register sets i/o for each pin of p0a. the port0b bit i/o selection register sets i/o for each pin of p0b. the port1b bit i/o selection register sets i/o for each pin of p1b. the port1c group i/o selection register sets i/o for each pin of p1c. the following explains the configuration and functions. b 3 b 2 b 1 b 0 000 p 1 c g i o b 3 b 2 b 1 b 0 p 1 b b i o 3 p 1 b b i o 2 p 1 b b i o 1 p 1 b b i o 0 b 3 b 2 b 1 b 0 p 0 b b i o 3 p 0 b b i o 2 p 0 b b i o 1 p 0 b b i o 0 b 2 b 1 b 0 p 0 a b i o 3 p 0 a b i o 2 p 0 a b i o 1 p 0 a b i o 0 b 3 27h 35h 36h 37h r/w r/w r/w r/w read/ write power-on clock stop ce 0000000000000000 0000000000000 0000000000000 0 1 register flag symbol port1c group i/o selection (p1cgpio) port1b bit i/o selection (p1bbio) port0b bit i/o selection (p0bbio) port0a bit i/o selection (p0abio) flag symbol flag symbol flag symbol address sets i/o of each general- purpose port port0a p0a 0 pin p0a 1 pin p0a 2 pin p0a 3 pin p0b 0 pin p0b 1 pin p0b 2 pin p0b 3 pin p1b 0 pin p1b 1 pin p1b 2 pin p1b 3 pin p1c 3 to p1c 1 pins port0b port1b port1c input port fixed at 0 output port at reset
196 m pd17062 15.3.4 to use an i/o port (p0a, p0b, p1b, p1c) as an input port select the pin to be used as an input port by using the i/o selection register of each port. p1c can be set to i/o in 3-bit (3-pin) units only. the pin specified as an input port enters floating (hi-z) status and waits for the input of an external signal. input data can be read by executing an instruction to read the contents of the port register for each pin, for example, the skt instruction. when a high level signal is input to each pin of the port register, 1 is read. when a low level signal is input to each pin of the port register, 0 is read. upon the execution of an instruction, such as the mov instruction, to write to the port register specified as an input port, the contents of the output latch are overwritten. 15.3.5 to use an i/o port (p0a, p0b, p1b, p1c) as an output port select the pin to be used as an output port by using the i/o selection register of each port. p1c can be set to i/o in 3-bit (3-pin) units only. the pin specified as an output port outputs the contents of the output latch from each pin. output data can be set by executing an instruction to write the contents of the port register for each pin, for example, the mov instruction. to output a high level signal to each pin, write 1. to output a low level signal to each pin, write 0. the pin can be set to the floating state (hi-z) by specifying it as an input port. upon executing an instruction, such as the skt instruction, for reading the port register specified as an output port, the contents of the output latch are read. note, however, that the contents of the output latch and the read contents may differ because the two pins, p0a 1 and p0a 0 , are read without changing the pin state. see section 15.3.6 .
197 m pd17062 15.3.6 notes on using i/o ports (p0a 1 and p0a 0 ) as shown in the example below, when pins p0a 1 and p0a 0 pins are used as output pins, the contents of the output latch may be overwritten. example: initflg not p0abio3, not p0abio2, p0abio1, p0abio0 ; set the p0a 1 , p0a 0 pins as output pins initflg not p0a3, not p0a2, p0a1, p0a0 ; # ; output a high level signal to the p0a 1 and p0a 0 pins clr1 p0a1 ; output a low level signal to the p0a 1 pin ; macro expansion and .mf.p0a1 shr 4, #.df. (not p0a1 and 0fh) if the p0a 0 pin is externally pulled down to the low level upon execution of instruction # , above, the clr1 instruction overwrites the contents of the output latch of the p0a 0 pin with 0. 15.3.7 state of i/o port (p0a, p0b, p1b, p1c) at reset (1) at power-on reset all i/o ports are set as input ports. since the contents of the output latch are indefinite, the output latch must be initialized by the program before the ports can be switched to output ports. (2) at ce reset all i/o ports are set as input ports. the contents of the output latch are retained. (3) at clock stop all i/o ports are set as input ports. the contents of the output latch are retained. in i/o ports other than p1c, the reset signal output at clock stop prevents the current drain from being increased by noise from the input buffer, as shown in section 15.3.1 . (4) during the halt state the previous state is retained.
198 m pd17062 15.4 general-purpose input port (p0d) 15.4.1 configuration the following explains the configuration of the input port. (1) p0d (p0d 3 , p0d 2 , p0d 1 , p0d 0 pins) 15.4.2 example of using input port (p0d) input data can be read by executing an instruction, such as the skt instruction, to read the contents of the port register for each pin. when a high level signal is input to each pin of the port register, 1 is read. when a low level signal is input to each pin of the port register, 0 is read. when a write instruction, such as the mov instruction, is executed, the port register remains as is. 15.4.3 notes on using input port (p0d) p0d is internally pulled down when being used as a general-purpose port. 15.4.4 state of input port (p0d) upon reset (1) at power-on reset all i/o ports are set as general-purpose input ports. (2) at ce reset all i/o ports are set as general-purpose input ports. (3) at clock stop all i/o ports are set as general-purpose input ports. the reset signal, output upon clock stop, prevents the current drain from increasing due to noise from the input buffer, as explained in section 15.4.1 . p0d is pulled down internally. (4) during halt state the previous state is retained. v dd reset adc selection signal write instruction to a/d converter high on-state resistor port register (1 bit) read instruction input latch
199 m pd17062 15.5 general-purpose output ports (p0c, p1a) 15.5.1 configuration of output ports (p0c, p1a) (1) and (2), below, show the configuration of the output ports. (1) p0c (p0c 3 , p0c 2 , p0c 1 , p0c 0 pins) (2) p1a (p1a 3 , p1a 2 , p1a 1 , p1a 0 pins) v dd output latch port register (1 bit) write instruction read instruction output latch port register (1 bit) write instruction read instruction
200 m pd17062 15.5.2 example of using output ports (p0c, p1a) the output ports output the contents of the output latch from each pin. output data can be set by executing an instruction, such as the mov instruction, to write the contents of the port register for each pin. to output a high level signal to each pin, write 1. to output a low level signal to each pin, write 0. however, the p1a 3 , p1a 2 , p1a 1 , and p1a 0 pins, because of the n-ch open-drain output, are set to the floating state (hi-z) when a high level signal is output. upon executing an instruction to read the port register, such as the skt instruction, the contents of the output latch are read. 15.5.3 state of output ports (p0c, p1a) at reset (1) at power-on reset the contents of the output latch are output. since the contents of the output latch are indefinite, indefinite values are output until the output latch is initialized by the program. (2) at ce reset the contents of the output latch are output. since the contents of the output latch are retained, the output data remains as is upon a ce reset. (3) at clock stop the contents of the output latch are output. since the contents of the output latch are retained, the output data remains as is at clock stop. therefore, the output latch must be initialized by the program as necessary. (4) during halt state the contents of the output latch are output. since the contents of the output latch are retained, the output data remains as is during the halt state.
201 m pd17062 16. serial interface the m pd17062 has two sets of serial interface pins, channel 0 (ch0) and channel 1 (ch1), for exchanging data with an external unit. the ch0 pin, which consists of two wires, sda and scl, can be operated in any of three modes, clock synchronous two-wire serial input, clock synchronous two-wire serial output, and two-wire bus note . the sda and scl pins can be used as general-purpose ports when not being used as a serial interface. the ch1 pin, which consists of three wires, sck, so, and si, can be operated in any of three modes, clock synchronous two-wire serial i/o input, clock synchronous two-wire serial i/o output, and three-wire serial i/ o. ch0 and ch1 cannot be operated at the same time. which of pins ch0 and ch1 is used is specified with the sio0ch flag (register file: 08h, b 3 ) of smode (serial interface mode register). the two-wire hardware-supported bus mode is for the single master. therefore, this mode does not support any arbitration function. arbitration must be done by the software. note the two-wire bus mode can be used as an i 2 c bus. table 16-1 external pins for serial interface 16.1 serial interface mode register the serial interface mode register specifies the operation mode of the serial interface. this register sets up the channel to be used, the protocol, clock, and transmission/reception. this register is mapped to address 08h in the register file. all flags of this register are set to 0 at power-on reset. fig. 16-1 configuration of serial interface mode register ch pin name function two-wire bus mode serial i/o mode port i/o setting register 0 p0a 0 /sda serial data i/o serial data i/o p0abio0 p0a 1 /scl shift clock i/o shift clock i/o p0abio1 1 p0a 2 /sck cannot be used shift clock i/o p0abio2 p0a 3 /so serial data output p0abio3 p0b 0 /si serial data input p0bbio0 bit position b 3 b 2 b 1 b 0 flag name sio0ch sb sio0ms sio0tx
202 m pd17062 table 16-2 ch0 operation modes remark : dont care serial interface port 0a i/o sda pin scl pin operation mode mode register specification sb sio0ms sio0tx p0abio0 p0abio1 0 0 0 0 0 sd-in ck-in serial i/o-si, ext-clk 0 0 0 0 1 sd-in out-port serial i/o-si, int-clk(soft-clk) 0 0 0 1 0 out-port in-port 1out-port+1in-port 0 0 0 1 1 out-port out-port 2out-port 0 0 1 0 sd-out ck-in serial i/o-so, ext-clk 0 0 1 1 sd-out out-port serial i/o-so, int-clk(soft-clk) 0 1 0 0 sd-in ck-out serial i/o-si, int-clk 0 1 0 1 out-port ck-out clk-out+1out-port 0 1 1 sd-out ck-out serial i/o-so, int-clk 1 0 0 0 0 sd-in ck-in bus-slave-rx 1 0 0 0 1 sd-in out-port bus-master-rx(soft-clk) 1 0 0 1 0 out-port in-port 1out-port+1in-port 1 0 0 1 1 out-port out-port 2out-port 1 0 1 0 sd-out ck-in bus-slave-tx 1 0 1 1 sd-out out-port bus-master-tx(soft-clk) 1 1 0 0 sd-in ck-out bus-master-rx 1 1 0 1 out-port ck-out clk-out+1out-port 111 sd-out ck-out bus-master-tx
203 m pd17062 table 16-3 ch1 operation modes remark : dont care serial interface port 0a i/o si pin sck pin so pin operation mode mode register specification sb sio0ms sio0tx p0abio2 p0abio3 p0bbio0 0 0 0 0 0 0 sd-in ck-in in-port serial i/o-si, ext-clk, 1in-port 0 0 0 0 0 1 sd-in ck-in out-port serial i/o-si, ext-clk, 1out-port 0 0 0 0 1 0 out-port in-port in-port 1out-port+2in-port 0 0 0 0 1 1 out-port in-port out-port 2out-port+1in-port 0 0 0 1 0 0 sd-in out-port in-port serial i/o-si, int-clk (soft-clk), 1in-port 0 0 0 1 0 1 sd-in out-port out-port serial i/o-si, int-clk (soft-clk), 1in-port 0 0 0 1 1 0 out-port out-port in-port 2out-port + 1in-port 0 0 0 1 1 1 out-port out-port out-port 3out-port 0 0 1 0 0 sd-in ck-in sd-out serial i/o-si/so, ext-clk 00 1 0 1 out-port ck-in sd-out serial i/o-so, ext-clk, 1out- port 00 1 1 0 sd-in out-port sd-out serial i/o-si/so, int-clk (soft- clk) 00 1 1 1 out-port out-port sd-out serial i/o-so, int-clk (soft-clk), 1out-port 0 1 0 0 0 sd-in ck-out in-port serial i/o-si, int-clk, 1in-port 0 1 0 0 1 sd-in ck-out out-port serial i/o-si, int-clk,1out-port 0 1 0 1 0 out-port ck-out in-port clk-out,1out-port, 1in-port 0 1 0 1 1 out-port ck-out out-port clk-out, 2out-port 0 1 1 0 sd-in ck-out sd-out serial i/o-si/so, int-clk 0 1 1 1 out-port ck-out sd-out serial i/o-so, int-clk, 1out-port 1 C C C not to be set
204 m pd17062 16.1.1 sio0ch the sio0ch flag is used to select the channel of the serial interface. when the sio0ch flag is set to 0, the serial interface hardware is connected to ch0. when the sio0ch flag is set to 1, the serial interface hardware is connected to ch1. the external pin of the unselected channels is used as a general-purpose port. table 16-4 channel setting of serial interface 16.1.2 sb the sb flag specifies the serial interface protocol. when the sb flag is set to 0, serial i/o mode is specified. when the sb flag is set to 1, two-wire bus mode is specified. since ch1 does not support two-wire bus mode, the sb flag must be set to 0 when ch1 is used. table 16-5 specification of serial interface protocol sio0ch channel to be selected 0 ch0 1 ch1 sb protocol 0 serial i/o mode 1 two-wire bus mode
205 m pd17062 16.1.3 sio0ms the sio0ms flag specifies the serial interface clock to be used. when the sio0ms flag is set to 0, the external clock is selected. when the sio0ms flag is set to 1, the internal clock is selected. when the internal clock is selected, its frequency is set by the shift clock frequency register (rf: 39h). when the sio0ms flag is set to 0 in two-wire bus mode, slave operation is specified. when the sio0ms flag is set to 1 in two-wire bus mode, master operation is specified. table 16-6 sio0ms flag functions 16.1.4 sio0tx if the sio0tx flag is set to 0 in two-wire bus mode, reception mode is specified. if the sio0tx flag is set to 1 in two-wire bus mode, transmission mode is specified. if the sio0tx flag becomes 0 upon specifying ch0 serial i/o mode, si mode (the sda pin is in input mode) is specified. if the sio0tx flag becomes 1 upon specifying ch0 serial i/o mode, so mode (the sda pin is in output mode) is specified. when the ch1 serial i/o mode is specified, the sio0tx flag specifies whether the so pin is to be used as a serial interface. when the sio0tx flag is set to 1, the so pin is used as an so pin. when the sio0tx flag is set to 0, the so pin is used as a general-purpose port. table 16-7 sio0tx flag functions sio0ms function 0 two-wire bus mode : slave operation serial i/o mode : external clock operation 1 two-wire bus mode : master operation serial i/o mode : internal clock operation sio0tx function 0 two-wire bus mode : rx (reception) mode ch0 serial i/o mode : si mode ch1 serial i/o mode : p0a 3 is used as a general-purpose port 1 two-wire bus mode : tx (transmission) mode ch0 serial i/o mode : so mode ch1 serial i/o mode : p0a 3 is used as an so pin
206 m pd17062 16.2 clock counter the clock counter is a wrap around counter that counts the clock of the shift clock pin (p0a 1 /scl pin for ch0, p0a 2 /sck pin for ch1) of the currently selected serial interface. the clock counter counts the shift clock from 1 to 9 repeatedly. the initial value of the counter is 0. the counter is incremented by 1 each time the clock rising edge is detected. once the counter has been incremented to 9, the counter is reset to 1, after which it is again incremented in the same way. in the following cases, the clock counter is reset to 0. (1) in two-wire bus mode (a) at power-on reset (b) when a stop instruction is executed and the system is clock stopped (c) when a start condition is detected (d) when the serial interface operation mode is switched from two-wire bus mode to serial i/o mode (2) in serial i/o mode (a) at power-on reset (b) when a stop instruction is executed and the system clock is stopped (c) when data is written into the wait register (d) when the serial interface operation mode is switched from serial i/o mode to two-wire bus mode whether the contents of the clock counter became 8 or 9 can be tested in the software by the status register. a request to stop the clock in either transmission mode or reception mode in two-wire bus mode can be handled by the wait register.
207 m pd17062 16.3 status register the status register is a four-bit read-only register that retains the start and stop states in two-wire bus mode and the contents of the current clock counter. fig. 16-2 configuration of status register 16.3.1 sbbsy (serial bus busy) flag the sbbsy flag, mapped to b 0 (lsb) of the status register (rf: 28h), detects the busy signal in two-wire bus mode. the sbbsy flag is valid only when two-wire bus mode is selected by the sb flag of the serial mode register. when the start condition is detected, the sbbsy flag is set to 1. when the stop condition is detected, the sbbsy flag is reset to 0. when serial i/o mode is selected by setting the contents of the serial mode register, the sbbsy flag is reset to 0 and remains set to 0 until two-wire bus mode is selected. this means that the sbbsy flag does not change in serial i/o mode. when neither transmission nor reception is performed, testing of the sbbsy flag in two-wire bus mode enables the system to determine whether other devices are communicating. 16.3.2 sbstt (serial bus start test) flag the sbstt flag, mapped to b1 of the status register, detects the start condition in two-wire bus mode. the sbstt flag is valid only when two-wire bus mode is selected by setting the sb flag of the serial mode register. when the start condition is detected, the sbstt flag is set to 1. when the contents of the clock counter become 9, the sbstt flag is reset to 0. 16.3.3 sio0sf9 (serial i/o shift 9 clock) flag the sio0sf9 flag, mapped to b 2 of the status register, is set to 1 when the contents of the clock counter become 9. when the contents of the clock counter become 0 or 1, the sio0sf9 flag is reset to 0. in master mode of two-wire bus mode, the contents of the flag that indicates whether the slave has returned an acknowledgement must be read after the sio0sf9 flag becomes 1 but before the flag becomes 1 again. the sio0sf9 flag is not influenced by the contents of the serial mode register. this means that the sio0sf9 flag is set when the contents of the clock counter become 9, even in serial i/o mode. bit position b 3 b 2 b 1 b 0 flag name sio0sf8 sio0sf9 sbstt sbbsy
208 m pd17062 16.3.4 sio0sf8 (serial i/o shift 8 clock) flag the sio0sf8 flag, mapped to b 3 of the status register, is set to 1 when the contents of the clock counter become 8. when the contents of the clock counter become 0 or 1, the sio0sf8 flag is reset to 0. an operation to read the presettable shift register must be performed while the sio0sf8 flag is set to 1. the sio0sf8 flag is not influenced by the contents of the serial mode register. fig. 16-3 sio0sf8 and sio0sf9 operations 6789123456789 scl, sck bit counter sio0sf8 sio0sf9
209 m pd17062 16.4 wait register the m pd17062 can set a state in which the serial interface hardware does not operate, even if a shift clock is input. this state is called wait mode and is set by the wait register. the wait register consists of four bits; the sio0wrq0 flag, which specifies the timing to stop (wait) serial interface communication, sio0wrq1 flag, sio0nwt flag, which indicates if whether the current state is waiting, and the sback flag, which indicates whether an acknowledgement is returned in two-wire bus mode. the wait register, mapped to the register file, is manipulated by executing peek and poke instructions via the window register. all flags of the wait register are reset to 0 at power-on reset and when the system clock is stopped by executing a stop instruction. fig. 16-4 configuration of wait register 16.4.1 sio0wrq1 and sio0wrq0 (serial i/o wait request) flag the sio0wrq1 and sio0wrq0 flags reserve (specify) the timing at which the serial interface hardware is forced to wait. the m pd17062 expands the concept of waiting from slave operations in two-wire bus mode, to the transmission side in two-wire bus mode and internal clock operations in serial i/o mode. during wait, the clock counter and the shift clock applied to the presettable shift register are disabled. this means that, during wait, the clock counter is not updated and the contents of the presettable shift register are not shifted, even if the level of the shift clock pin changes. bit position b 3 b 2 b 1 b 0 flag name sback sio0nwt sio0wrq1 sio0wrq0
210 m pd17062 table 16-8 wait timings (1) slave operation wait in two-wire bus mode when the timing specified by sio0wrq1 and sio0wrq0 is set, the scl pin is switched to output mode and a low level signal is output. if no-wait (sio0wrq1 = sio0wrq0 = 0) is specified, this operation is not performed. wait is released by writing 1 into the sio0nwt flag of the wait register. for example, if 1 is written into the sio0nwt flag of the wait register while waiting with the data wait mode (sio0wrq1 = 0, sio0wrq0 = 1: waits when the shift clock falls with the clock counter set to 8) specified, wait is released. when the shift clock falls with the clock counter set to 8 again, the slave operation waits again. if communication has not started in slave operation, ordinary address wait mode (sio0wrq1 = sio0wrq0 = 1) is specified. in this wait mode, the slave operation waits when the shift clock falls, with the clock counter at set to 8, the first time after detection of the start condition. this means that, in this mode, the slave operation waits before the ninth clock (for acknowledgment of transmission of the slave address) rises. while the slave operation waits in this mode, the contents of the presettable shift register (psr) are read to determine whether the address is mapped to the local station. testing the sio0nwt flag enables the system to determine whether the slave operation is waiting. sio0wrq1 sio0wrq0 wait mode two-wire bus mode serial i/o mode 0 0 no-wait does not wait. does not wait. 0 1 data wait waits when the shift clock falls waits with the shift clock in the with the clock counter set to 8. high level state when the contents of the clock counter become 8. 1 0 acknowledge wait waits when the shift clock falls waits with the shift clock in the with the clock counter set to 9. high level state when the contents of the clock counter become 9. 1 1 address wait waits when the shift clock falls not to be set with the clock counter set to 8 after detection of the start condition.
211 m pd17062 (2) master operation wait in two-wire bus mode master operation wait in two-wire bus mode incurs the interruption of transmission. in this mode, when the timing specified by sio0wrq1 and sio0wrq0 is set, the shift clock is fixed to the low level. for example, testing the flag enables the system to determine whether the receiver has returned an acknowledgement while waiting with the acknowledge wait mode (sio0wrq1 = 1, sio0wrq0 = 0: waits when the shift clock falls with the clock counter set to 9) specified. while waiting in this mode, data to be transmitted next can be set in the presettable shift register. wait is released by writing 1 into the sio0nwt flag, in exactly the same way as for a slave operation. if no-wait is specified, this operation is not performed. (3) internal clock operation wait in serial i/o mode this wait mode is almost the same as wait in two-wire bus mode. this wait also incurs the interruption of transmission. the only difference is that the master operation waits with the shift clock set to low level in two-wire bus mode while the internal clock operation waits with the shift clock set to the high level in serial i/o mode. if serial i/o mode is specified, the clock counter is reset to 0 by performing a data write operation on the wait register. for this reason, if data wait mode is specified then acknowledge wait mode is respecified, the clock counter starts counting after being reset to 0 and the shift clock stops at the high level when the clock counter reaches 9. this means that, in internal clock operation mode of serial i/o mode, writing data into the wait register resets the clock counter, after which transmission starts. if no-wait is specified, the shift clock is output continuously. (4) external clock operation wait in serial i/o mode for external clock operation in serial i/o mode, update of the clock counter and shift of the presettable shift register are prohibited at the timing specified by sio0wrq1 and sio0wrq0. for example, if data wait mode is specified, the external clock waits when the clock falls with the clock counter set to 8. and, the clock counter is subsequently not updated by the shift clock input, nor does the presettable shift register shift data. to enable data after waiting, 1 must be written into the sio0nwt flag as usual. this means that the clock counter is reset to 0 by writing data into the wait register, after which wait is released.
212 m pd17062 16.4.2 sio0nwt (serial i/o no-wait) flag writing appropriate data into the sio0nwt flag can both release wait and execute forced wait. (1) writing 0 into sio0nwt in this case, forced wait is executed. in other words, the clock being supplied to the clock counter and presettable shift register is disabled. if the sio0ms flag of the serial interface mode register is set to 1 at this time, shift clock operation stops in the current state. (2) writing 1 into sio0nwt in this case, wait is released. in other words, the clock being supplied to the clock counter and presettable shift register is enabled. if the sio0ms flag of the serial interface mode register is set to 1 at this time, the shift clock operation resumes from the state existing immediately before waiting began. 16.4.3 sback (serial bus acknowledge) the operation of sback varies with the operation mode of the serial interface. the following describes the operation of sback. (1) for reception in two-wire bus mode (sio0tx = 0) in this case, the data set in the sback flag is automatically output to the sda pin at the acknowledge output timing. the contents of the sback flag can be changed only by executing poke instruction on the wait register. for this reason, to return acknowledgement continuously, simply write 0 into the sback flag. then, 0 is automatically transmitted as an acknowledgement. this eliminates the need to manipulate the sback flag each time 1-byte data is received. data must be written to the sback flag after the 9th bit of the data has been set but before the 9th bit of the next data is set. normally, wait is instigated at the falling edge of the 8th or 9th bit. therefore, data should be written into the sback flag at this time. fig. 16-5 timing of sback rewriting during wait 567 8 9 scl clock counter sda sback=1 sback=0 sback ? 0 sio0nwt ? 1 wait
213 m pd17062 (2) for transmission in two-wire bus mode (sio0tx = 1) in this case, the contents of an acknowledgement received from the receiver side are set in the sback flag. this means that the acknowledge state of the receiver side can be determined simply by reading the contents of the sback flag. this examining of the sback flag must be done after the 9th bit of 1-byte is set but before the 9th bit of the next data is set. normally, waiting is instigated at the falling edge of the 9th bit. therefore, the sback flag must be read at this time. data can be written into the sback flag by executing a poke instruction, even during transmission. (3) in serial i/o mode in this case, the contents of the sback flag are not influenced by the shift clock. in other words, the sback flag is completely isolated from the serial interface. hence, sback can be used as a 1-bit flag for data storage.
214 m pd17062 16.5 presettable shift register (psr) the presettable shift register is an 8-bit register. it outputs the contents of the most significant bit of the psr to the serial data output pin (p0a 0 /sda pin for ch0, p0a 3 /so pin for ch1) synchronously with the falling edge of the clock signal on the shift clock pin (p0a 1 /scl pin for ch0, p0a 2 /sck pin for ch1) and reads the data of the serial data input pin (p0a 0 /sda pin for ch0, p0b 0 /si pin for ch1) into the least significant bit of the psr synchronously with the rising edge of the clock. in the wait state, the shift clock is not supplied to psr. in other words, the psr does not shift data in the wait state even if a clock (internal or external) is supplied to the shift clock pin (internally or externally) . the operation of the psr that is not in the wait state varies between two-wire bus mode and serial i/o mode. data is written to the psr by the put instruction and read from the psr by the get instruction via the 8 low-order bits (data memory address: 0eh, 0fh) of dbf in data memory. (1) psr operation in two-wire bus mode if two-wire bus mode is specified, the shift clock is supplied to the psr only while the clock counter is set to 1 to 8. for example, to receive 9-bit data (8-bit data + 1-bit acknowledgement) in two-wire bus mode, the first 8 bits of data are read into the psr. then, the 9th bit is read into the sback flag of the wait register. when the contents of the psr are transmitted in two-wire bus mode, the contents of the psr are output to the serial data pin while the clock counter is set to 1 to 8, and the contents of the sback flag are output while the clock counter is set to 9 (more precisely, between the fall of the 8th bit clock to the rise of the 9th bit clock). the psr operates as described above not only when using the hardware of the serial interface of the m pd17062 (also when using internal or external clock) but also when the clock is generated by the software with the port (p0a 0 ) also used as the shift clock pin set as an output port. during transmission, data output to the sda pin is again read into the psr synchronously with the rise of the next shift clock. therefore, in transmission also, once the shift clock has been output 8 times, data on the pin being transmitted is stored in the psr. if no data conflict occurs during transmission, the data stored into the psr will be exactly the same as that before the transmission. hence, the data before transmission and psr data after transmission can be compared to determine whether the data was transmitted normally. the above explanation applies to a psr that is not in the wait state, the psr does not perform any shift operations. (2) psr operation in serial i/o mode when serial i/o mode is specified, the shift clock supply to the psr is not related to the contents of the clock counter. the psr performs a shift operation according to the clock in the shift clock pin unless it is currently in the wait state. the psr does not perform any shift operations in the wait state. hence, when the psr is used merely for data storage, not as a serial interface, the psr must be set to the wait state. in serial i/o mode, data must be written to the psr or read from the psr when the shift clock is at the high level or in the wait state. if data is written or read at any other time, the psr will not operate normally. normally, when the internal clock is used, wait should occur with the rise of the 8th bit clock, and the psr should be manipulated during this wait state. when the external clock is used, the psr should be manipulated while the high level of the shift clock is checked by the transmission side.
215 m pd17062 16.6 serial interface interrupt source register (sio0imd) the interrupt source register (sio0imd) is a four-bit register that specifies when an interrupt is generated in the cpu during serial interface communication. the sio0imd register is mapped to address 38h of the register file. fig. 16-6 shows the configuration of the sio0imd register. the register is not mapped to the two high-order bits of the sio0imd. if the two high-order bits of the sio0imd are read, 0 is read from each bit. fig. 16-6 configuration of serial interface interrupt source register (rf: 38h) table 16-9 functions of serial interface interrupt source register sio0imd1 sio0imd0 function 0 0 an interrupt request is generated when the 7th bit of the shift clock rises. 0 1 an interrupt request is generated when the 8th bit of the shift clock falls. 1 0 an interrupt request is generated at the rising edge of the 7th bit of the shift clock immediately after detection of the start condition. 1 1 an interrupt request is generated upon detection of the stop condition. bit position b 3 b 2 b 1 b 0 flag name sio0imd3 sio0imd2 sio0imd1 sio0imd0 (0) (0)
216 m pd17062 bit position b 3 b 2 b 1 b 0 flag name sio0ck3 sio0ck2 sio0ck1 sio0ck0 (0) (0) sio0ck1 sio0ck0 internal clock frequency 0 0 100 khz 0 1 200 khz 1 0 500 khz 1 1 1 mhz 16.7 shift clock frequency register (sio0ck) the shift clock frequency register is a four-bit register for setting the frequency of the internal clock of the serial interface. the shift clock frequency register is mapped to address 39h of the register file. fig. 16-7 shows the configuration of the shift clock frequency register. the register is not mapped to the two high-order bits of the shift clock frequency register. if the two high-order bits of the shift clock frequency register are read, 0 is read from each bit. fig. 16-7 configuration of shift clock frequency register (rf: 39h) table 16-10 internal clock frequencies of serial interface
217 m pd17062 peripheral equipment peripheral address corresponding pin pwm0 05h pwm 0 pwm1 06h pwm 1 pwm2 07h pwm 2 pwm3 08h pwm 3 17. d/a converter 17.1 pwm pins the m pd17062 has 4 output pins for 6-bit pwm, which enables varying the duty cycle of the 15.625 khz pulse signal in 64 steps. with this capability, attaching an external lowpass filter to the m pd17062 makes it function as a d/a converter. the pwm pins can also be used as 1-bit output ports. when used as a d/a converter, the m pd17062 sets the d/a outputs in the output data latches, pwmrs. these latches, pwmr0, pwmr1, pwmr2, and pwmr3, are mapped at addresses 05h, 06h, 07h, and 08h, respec- tively. they can be read- and write-accessed via the dbf. table 17-1 lists the correspondence between the pwmr addresses and the pwm pins. table 17-1 pwmr addresses and the corresponding pins each pwmr consists of 7 bits. fig. 17-1 shows the configuration of the pwmr and its correspondence with the dbf. the highest bit of the pwmr specifies whether the pwm pin is to be used as a pwm output pin or an output port. the other six bits specify the output values of the pwm signal. fig. 17-2 shows the waveform output from the pwmr pin.
218 m pd17062 fig. 17-1 pwmr structure and the corresponding dbf bits fig. 17-2 waveform output from the pwm pin b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 1 pwmr dbf1 (0eh) dbf0 (0fh) the pwm pin is used as a d/a converter. the pwm pin is used as a one-bit output port (through mode), which outputs the content of b 5 . t 64 s t = n + 0.75 ( s) (where n is a value specified in the pwmr) m m
219 m pd17062 18. pll frequency synthesizer 18.1 pll frequency synthesizer configuration fig. 18-1 is a block diagram of the pll frequency synthesizer. as shown in fig. 18-1, the pll frequency synthesizer consists of a programmable divider (pd), phase comparator ( f -det), reference frequency generator (rfg), and charge pump. strictly speaking, a pll frequency synthesizer is configured by connecting these blocks with an external lowpass filter (lpf) and voltage-controlled oscillator (vco). see sections 18.3 to 18.5 for details of these blocks. fig. 18-1 pll frequency synthesizer block diagram note external circuit vco psc eo register data buffer unlock detection block programmable divider (pd) phase comparator ( -det) f charge pump reference frequency generator (rfg) prescaler p b595 note note voltage-controlled oscillator (vco) lowpass filter (lpf) note m
220 m pd17062 18.2 overview of each pll frequency synthesizer block the pll frequency synthesizer receives an input signal at the vco pin, divides its frequency in the programmable divider, and outputs the difference in phase between the divider output and the reference frequency from the eo pin. the pll frequency synthesizer works only when the ce pin is at a high level. it is disabled when the ce pin is at a low level. see section 18.6 for the disable mode of the pll frequency synthesizer. items (1) to (4) briefly describe each block of the synthesizer. (1) programmable divider (pd) the programmable divider divides the frequency of a signal input from the vco pin. it uses necs proprietary pulse swallow method to divide a frequency. a division value is given through the data buffer (dbf). see section 18.3 . (2) reference frequency generator (rfg) the reference frequency generator generates a reference frequency that the phase comparator ( f -det) uses for reference purposes. a reference frequency can be selected using the pll reference mode select register (at address 13h). see section 18.4 . (3) phase comparator ( f -det) and unlock detection block the phase comparator compares the output signal of the programmable divider (pd) with a signal from the reference frequency generator (rfg) and outputs the phase difference between the signals. the phase comparator can also detect the pll unlock state. detection of the pll unlock state is controlled with the pll unlock ff delay control register (at address 32h) and the pll unlock ff judge register (at address 22h). see section 18.5 . (4) charge pump the charge pump directs the output signal of the phase comparator ( f -det) to the eo pin as a high, low level, or floating output. see section 18.5 .
221 m pd17062 18.3 programmable divider (pd) and pll mode select register 18.3.1 programmable divider configuration fig. 18-2 shows the configuration of the programmable divider (pd). as shown in fig. 18-2, the programmable divider consists of a swallow counter and programmable counter. fig. 18-2 programmable divider configuration 0ch 0dh 0eh 0fh dbf3 dbf2 dbf1 dbf0 m s b l s b 16 12 4 psc vco data buffer (dbf) address symbol data pll data register 12 bits 4 bits swallow counter 4 bits programmable counter 12 bits f n to -det f 1/2 frequency divider pll disable signal
222 m pd17062 18.3.2 programmable divider (pd) and data buffer (dbf) the programmable divider divides the frequency of an input signal at the vco pin by the values specified in the swallow counter and programmable counter. the swallow and programmable counters consist of a 4- and 12-bit binary downcounter, respectively. the swallow and programmable counters are loaded with a division value by setting it in the pll data register (pllr, at address 41h) through the data buffer (dbf). writing to and reading from the pll data register are performed with the put pllr,dbf and get dbf,pllr instructions respectively. a division value is called an n-value. the following expression represents the frequency f n of a signal generated in the programmable divider using the value n in the pll data register (pllr). pulse swallow method f n = f in (where n is 16 bits) n see section 18.7 for how to set the division value (n-value) for each frequency division method.
223 m pd17062 18.4 reference frequency generator (rfg) 18.4.1 reference frequency generator (rfg) configuration and functions fig. 18-3 shows the configuration of the reference frequency generator. as shown in fig. 18-3, the reference frequency generator divides the frequency of the clock oscillator (8 mhz) to generate the reference frequency f r for the pll frequency synthesizer. the reference frequency f r can be selected from 6.25, 12.5, and 25 khz. selection of the reference frequency f r is performed using the pll reference mode select register (at address 13h). section 18.4.2 describes the configuration and functions of the pll reference mode select register. fig. 18-3 reference frequency generator (rfg) configuration 13h b 3 b 2 b 0 b 1 p l l r f c k 3 p l l r f c k 2 p l l r f c k 0 p l l r f c k 1 8 mhz 6.25 khz 12.5 khz 25 khz off control register address bit flag symbol multiplexer pll disable signal to -det f divider
224 m pd17062 18.4.2 pll reference mode select register configuration and functions fig. 18-4 shows the configuration and functions of the pll reference mode select register. when the pll reference mode select register selects the pll disable mode, the vco pin is pulled down internally, and the eo pin floats. see section 18.6 for the pll disable mode. fig. 18-4 pll reference mode select register configuration and functions b 3 b 2 b 1 b 0 p l l r f c k 3 p l l r f c k 2 p l l r f c k 1 p l l r f c k 0 13h read/write r/w except pllrfck1, which is read-only 0010 0011 0110 1111 0111 1010 1011 1110 6.25 khz 12.5 khz 25 khz 1111 1111 ce register address flag symbol pll reference mode select (plrfmode) specify the reference frequency f r for the pll frequency synthesizer. pll disable not to be set fixed at 1 upon reset clock stop power-on kept unchanged
225 m pd17062 18.5 phase comparator ( f -det), charge pump, and unlock detection block 18.5.1 configuration of the phase comparator ( f -det), charge pump, and unlock detection block fig. 18-5 shows the configuration of the phase comparator ( f -det), charge pump, and unlock detection block. the phase comparator compares the phase of the output frequency f n of the programmable divider (pd) with the reference frequency output f r of the reference frequency generator, and outputs the up request signal (up) or down request signal (dw). the charge pump directs the output of the phase comparator to the error output pin (eo pin). the unlock detection block consists of a delay control circuit and unlock flip-flop (ff). it detects the unlock state of the pll frequency synthesizer. sections 18.5.2 , 18.5.3 , and 18.5.4 explain the operation of the phase comparator, charge pump, and unlock detection block, respectively. fig. 18-5 configuration of the phase comparator, charge pump, and unlock detection block 32h 22h b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 p l u l s e n 3 p l u l s e n 2 p l u l s e n 1 p l u l s e n 0 000 p l l u l control register eo v dd p-ch n-ch up dw f r f n address bit flag symbol unlock detection block delay control unlock ff charge pump reference frequency generator programmable divider pll disable signal phase comparator ( -det) f
226 m pd17062 18.5.2 functions of the phase comparator ( f -det) as shown in fig. 18-5, the phase comparator compares the phase of the output frequency f n of the programmable divider (pd) and the phase of the reference frequency f r , and outputs the up request signal (up) or down request signal (dw). if the divider output frequency f n is lower than the reference frequency f r , the phase comparator outputs an up request. if f n is higher than f r , the phase comparator outputs a down request. fig. 18-6 shows the relationship among the reference frequency f r , divider output frequency f n , up request up, and down request dw. in the pll disable mode, neither up nor down request is output. the up and down requests are directed to the charge pump and unlock detection block.
227 m pd17062 fig. 18-6 relationship among f r , f n , up, and dw signals (1) when f n is lagging behind f r (2) when f n is leading f r (3) when f n is in phase with f r (4) when f n is lower than f r f r f n up dw ? f r f n up dw ? f r f n up dw ? ? f r f n up dw ?
228 m pd17062 18.5.3 charge pump as shown in fig. 18-5, the charge pump directs the up request signal (up) or down request signal (dw) from the phase comparator ( f -det) to the error output pin (eo) pin. the relationships among the output at the error output pin, divider output frequency f n , and reference frequency f r are as follows: reference frequency f r > divider output frequency f n : low level output reference frequency f r < divider output frequency f n : high level output reference frequency f r = divider output frequency f n : floating 18.5.4 unlock detection block as shown in fig. 18-5, the unlock detection block detects the unlock state of the pll frequency synthesizer according to the up request signal (up) or down request signal (dw) from the phase comparator ( f -det). either the up or down request signal is low in the unlock state. so the unlock detection block detects this low signal as unlock state. when the unlock state is detected, the unlock flip-flop (ff) is set (1). the state of the unlock ff is detected using the pll unlock ff judge register (at address 22h). the unlock ff is set at intervals of the then selected reference frequency f r . the unlock ff is reset when the pll unlock ff judge register is read-accessed with a peek instruction. the unlock ff must be checked at intervals greater than the period (1/f r ) of the reference frequency f r . the unlock delay control circuit controls whether to set the unlock ff, by delaying the up and down request signals output from the phase comparator. if the delay becomes large, the unlock ff will not be set even if the phase difference between the divider output frequency f n and reference frequency fr is large. the delay is specified in the unlock delay control circuit using the pll unlock ff delay control register (at address 32h). the following paragraphs describe the configuration and functions of the pll unlock ff judge register and pll unlock ff delay control register.
229 m pd17062 (1) pll unlock ff judge register (plluljdg) this register is a read-only register. it is reset when its content is read into a window register (wr) with a peek instruction. because the unlock ff is set at intervals of the period (1/f r ) of the reference frequency f r , the content of this register must be read into the window register at intervals larger than the period of the reference frequency. fig. 18-7 configuration and functions of the pll unlock ff judge register (plluljdg) remark the plluljdg is reset when it is read-accessed with a peek instruction. register flag symbol b 3 b 2 b 1 b 0 p l l u l 22h r address read/write upon reset power-on clock stop ce 00 0 1 detects the state of the unlock ff. unlock ff = 0 : pll locked unlock ff = 1 : pll unlocked 0 * 0 fixed to 0. pll unlock ff judge register (plluljdg) 0 0 * undefined hold hold
230 m pd17062 (2) pll unlock ff delay control register (plulsen) when the unlock ff disable mode is selected, the unlock ff remains set. so, note that if the pll unlock ff judge register checks the unlock ff in the unlock ff disable mode, it always appears to be unlocked (pllul flag = 1). fig. 18-8 configuration and functions of the pll unlock ff delay control register (plulsen) p l u l s e n 3 register flag symbol b 3 b 2 b 1 b 0 p l u l s e n 1 p l u l s e n 0 32h r/w address read/write 0 upon reset power-on clock stop ce 00 0 01 10 11 1.25-1.5 s or more 3.5-3.75 s or more 0.25-0.5 s or more unlock ff disabled (always to be set) 00 00 hold sets the delay time between the reference (f r ) and division frequency (f n ) signals, which is necessary to set the unlock ff. fixed to 0. pll unlock ff delay control (plulsen) hold p l u l s e n 2 m m m
231 m pd17062 18.6 pll disable mode the pll frequency synthesizer is disabled when the ce pin is at a low level. it is also disabled when the pll reference mode select register (plrfmode, at address 13h) selects the pll disable mode. table 18-1 summarizes how each block operates during the pll disable mode. because the pll reference mode select register is not initialized at a ce reset (its previous state is preserved), it returns to the previous state after the ce pin goes low (selecting the pll disable mode) then back to a high. if it is necessary to select the pll disable mode at a ce reset, the pll reference mode select register should be initialized by program. the pll frequency synthesizer is disabled at a power-on reset. table 18-1 operation of each block during the pll disable mode block ce pin = low or plrfmode = 1111b vco pin pulled down internally programmable counter frequency division disabled reference frequency generator output disabled phase comparator output disabled charge pump error output pin floating
232 m pd17062 pllr 0000 0110 1100 1111 06 cf plrfmode 0010 6.25 khz 18.7 setting data for the pll frequency synthesizer the following data is necessary to control the pll frequency synthesizer. (1) reference frequency : f r (2) division value : n the following paragraphs explain how to set the pll data. (1) setting reference frequency f r the reference frequency is specified according to the pll reference mode select register. (2) calculating division value n the division value n is calculated as follows: n = f uco p f r where f uco : frequency input to the vco pin f r : reference frequency p : prescaler frequency division ratio (3) example of setting the pll data the following example shows how to specify the data required to receive channel 02 of the west europe tv system, assuming that the prescaler used here is the m pb595 and that the frequency division ratio p is 8. receive frequency : 48.25 mhz reference frequency : 6.25 khz intermediate frequency : 38.9 mhz the division value n is calculated as follows: n = f uco = 48250 + 38900 = 1743 (decimal) p f r 8 6.25 = 06cfh (hexadecimal) the pll data register (pllr, at address 41h) and pll reference mode select register (plrfmod, at address 13h) are set with data as shown below.
233 m pd17062 19. a/d converter the m pd17062 contains a 4-bit program-controlled a/d converter that operates with a successive compari- son method. 19.1 principle of operation the a/d converter in the m pd17062 consists of a 4-bit resistor string-based d/a converter and comparator. the d/a converter is set with data using a 4-bit register (adcr) mapped at peripheral address 02h. the result of comparison is judged according to the adccmp flag in the register file. fig. 19-1 a/d converter configuration adcch adcch adcch ad 2 1 0 ccmp adcr d/a converter channel selector rf : 21h adcch (r/w) adccmp (r) comparator adc0 adc1 adc2 adc3 adc4 adc5 peripheral address: 02h adcr (r/w)
234 m pd17062 19.2 d/a converter configuration the d/a converter used in the a/d converter of the m pd17062 is a resistor string d/a converter consisting of 16 resistors connected in series between the v dd and gnd pins in which a voltage at each resistor connection point is selected. the configuration of the d/a converter is shown in fig. 19-2. fig. 19-2 d/a converter configuration with the configuration shown above, the d/a converter outputs a ground level when the adcr is set with value 0000b. it also outputs 1/32 v dd when the adcr is set with 0001b. the following expression represents the reference voltage v ref that the d/a converter outputs when the adcr is set with value n (decimal). v ref = v dd 2n C 1 (where 15 3 n 3 1) 32 table 19-1 d/a converter reference voltage adcr 4 01 2 131415 selector 1/2r r r r r r 3/2r v dd d/a output (reference voltage) set data (adcr) reference voltage (v ref ) hexadecimal binary v dd v dd = 5 v 0 0000 0 0 [v] 1 0001 1/32 0.15625 2 0010 3/32 0.46875 3 0011 5/32 0.78125 4 0100 7/32 1.09375 5 0101 9/32 1.40625 6 0110 11/32 1.71875 7 0111 13/32 2.03125 8 1000 15/32 2.34375 9 1001 17/32 2.65625 a 1010 19/32 2.96875 b 1011 21/32 3.28125 c 1100 23/32 3.59375 d 1101 25/32 3.90625 e 1110 27/32 4.21875 f 1111 29/32 4.53125
235 m pd17062 19.3 reference voltage setting register (adcr) the adcr is a 4-bit register to specify a reference voltage for the a/d converter. it is mapped at peripheral address 02h. data is written to and read from the adcr register through the data buffer using the put and get instructions respectively. the data transfer between the adcr and dbf is performed in 8-bit units although the adcr is a 4-bit register. in other words, 8-bit data is transferred through the dbf1 (0eh) and dbf0 (0fh). to be specific, when the get dbf, adcr instruction is executed to read from the adcr register, the content of the adcr is sent to the dbf0 and 0000b is sent to the dbf1. similarly, when the put adcr, dbf instruction is executed, the data in the dbf0 is sent to the adcr; the dbf1 may contain any data. the adcr is undefined at power-on. at a clock stop and ce reset, it retains the previous data. 19.4 comparison register (adccmp) the adccmp is a register that holds the output of a comparator which compares an input voltage at the adc pin with the reference voltage (v ref ). it is mapped at bit b0 (lsb) of the register file at address 21h. the adccmp is a 1-bit read-only register; it cannot be written to. the peek instruction is executed to read data from the adccmp into a window register. at this point, the adc pin select data is also read into the upper 3 bits of the window register. the window register will receive the adccmp content as follows: adccmp = 0 when input voltage < reference voltage adccmp = 1 when input voltage 3 reference voltage
236 m pd17062 b 3 b 2 b 1 #0 (msb) (lsb) (rf : 21h) adccmp adcch2 adcch1 adcch0 selected pin 0 0 0 adc 0 0 0 1 p1c 3 /adc 1 0 1 0 p0d 0 /adc 2 0 1 1 p0d 1 /adc 3 1 0 0 p0d 2 /adc 4 1 0 1 p0d 3 /adc 5 110 no corresponding pin (do not set) 111 19.5 adc pin select register (adcchn) the adcchn register selects an a/d converter input pin. it is mapped at the upper 3 bits of the register file at address 21h. table 19-2 lists the relationships between the adcchn and the actually selected pins. table 19-2 adc pin selection when using p1c 3 /adc 1 as the a/d converter, specify the p1c as an input port. the p0d 0 /adc 2 to p0d 3 /adc 5 pins are internally equipped with pull-down resistors, but the pull-down resistors are disconnected when they are selected as the a/d converter. if p1c and p0d pins selected as the a/d converter are accessed as ports, 0 is read out.
237 m pd17062 19.6 example of a/d conversion program the following example shows an a/d conversion program based on the successive comparison method. the result of conversion is held in the dbf0. sample program dbf0b3 flg 0.0fh.3 dbf0b2 flg 0.0fh.2 dbf0b1 flg 0.0fh.1 dbf0b0 flg 0.0fh.0 start: bank0 initflg dbf0b3, not dbf0b2, not dbf0b1, not dbf0b0 ; sets dbf data. put adcr, dbf ; sets reference voltage. skt1 adccmp ; judges comparison result. clr1 dbf0b3 ; dbf0b3 ? 0 set1 dbf0b2 ; dbf0b2 ? 1 put adcr, dbf ; sets reference voltage. skt1 adccmp ; judges comparison result. clr1 dbf0b2 ; dbf0b2 ? 0 set1 dbf0b1 ; dbf0b1 ? 1 put adcr, dbf ; sets reference voltage. skt1 adccmp ; judges comparison result. clr1 dbf0b1 ; dbf0b1 ? 0 set1 dbf0b0 ; dbf0b0 ? 1 put adcr, dbf ; sets reference voltage. skt1 adccmp ; judges comparison result. clr1 dbf0b0 ; dbf0b0 ? 0 end: number of steps in the conversion loop : 17 conversion time : 34 m s (not in dma mode) conversion time : 204 m s (in dma mode)
238 m pd17062 flowchart start dbf ? 1000b adcr ? dbf adccmp dbf0b3 ? 0 dbf0b2 ? 1 adcr ? dbf adccmp 1 0 1 0 dbf0b2 ? 0 dbf0b1 ? 1 1 sets dbf data. begins ad conversion. judges comparison result. dbf0b3 ? 0 dbf0b2 ? 1 judges comparison result. sets reference voltage. sets reference voltage. dbf0b2 ? 0 dbf0b1 ? 1
239 m pd17062 end adcr ? dbf adccmp dbf0b1 ? 0 dbf0b0 ? 1 adcr ? dbf adccmp 1 0 1 0 dbf0b0 ? 0 dbf0b0 ? 0 dbf0b1 ? 0 dbf0b0 ? 1 1 sets reference voltage. judges comparison result. sets reference voltage. judges comparison result.
240 m pd17062 tv screen 19 characters 14 rows 20. image display controller the image display controller (idc) function indicates a channel number, volume of sound, time, and other information on a tv screen. the pattern of a display is user-programmable, and the display pattern definition is stored in the crom area. the pattern to be actually displayed is stored in vram, which is mapped at bank1 and bank2 in data memory. 20.1 specification overview and restrictions (1) maximum number of characters that can be displayed on one screen: 97 this specification applies when one control code is used per row. the maximum number of characters that can be displayed on one screen varies with the number of times control data is used. using the control data three times per row amounts to that it is possible to specify the color three times per row. (2) variable display position range: 19 characters 14 rows the display area is defined for the tv screen as follows: (3) up to 8 colors (including black and white) can be specified for individual characters. independent specification of r, g, and b (using control data note ) note up to three control data items can be specified per row. character size maximum number of number of times that display characters per row control data is used per row standard (minimum) 19 up to 3 double size 9 up to 6 triple size 5 up to 5 quadruple size 4 up to 4
241 m pd17062 (4) rounding, rimming, and reverse video can be specified for individual characters. (5) number of fonts: 120 (user-programmable) the number of fonts that can be displayed on one screen simultaneously is limited to within 64. character pattern data is located in program memory (crom), and up to 120 character patterns can be specified; however, up to 64 character patterns (in the same crombank) can be displayed on one screen simultaneously. no rimming rimming rounding reverse video color specification by r, g, and b blank (black) background (tv screen) 0 0 0 0 h 0 0 f f h 0 1 0 0 h 0 7 f f h 0 8 0 0 h 0 b f f h 0 c 0 0 h 0 f 7 f h rom map crombank0 64 fonts crombank1 56 fonts characters defined in crombank0 cannot be displayed together with those in crombank1 on the same screen.
242 m pd17062 (6) up to 4 different character sizes, both vertical and horizontal, are available. the same vertical character size is specified for all characters in a row, while the horizontal character size is specified for individual characters (according to the control data note 1 ). (7) the character bit configuration is 10 15 dots. there is no gap between character positions. note 2 (8) character pattern data is allocated in program memory. if there is only a small amount of character pattern data, the crom area can also be used as a program area. (9) character data is allocated in the data memory space. the character data can be transferred, read, and written in the same manner as ordinary data in data memory. notes 1. up to three control data items can be specified per row. 2. because there is no gap between character positions, kanji and other graphic images can be defined by combining two or more predefined characters.
243 m pd17062 20.2 direct memory access the direct memory access (dma) function transfers memory contents directly to peripheral equipment, without using the cpu. in the m pd17062, the dma mode is used to run the idc. the instruction cycle of the m pd17062 is 2 m s, but its apparent instruction cycle becomes 12 m s during the dma mode. this does not mean that the actual instruction cycle becomes 12 m s, but means that data transfer for the idc takes 10 m s (5 instruction cycles) and execution of an instruction takes one instruction cycle as usual. during dma mode, instructions are executed at every five instruction cycles. for the above reason, execution of one instruction takes 12 m s apparently when the idc is being used. in a program in which a problem may occur if 12 m s and 2 m s instruction cycles are mixed, the idc must be kept at a stop and the dma mode can be specified only for critical sections of the program. in this case, during five instruction cycles for idc data transfer, only the clock operates, and the m pd17062 does nothing. during the dma mode, the rom address for five instructions out of the six is not pointed to by the program counter. instead, it is pointed to by the crom address pointer, and the ram address is pointed to by the vram address pointer. the dma mode is controlled using the idcdmaen flag. the idcdmaen flag is mapped at the register file. it is a one-bit flag that can be both read- and write- accessed. when this flag is set, a dma request is accepted to begin the dma mode in preference to any other interrupt request. when the idcdmaen flag is reset, no dma request is accepted. if it is reset during the dma mode, the dma mode is terminated upon completion of the instruction that resets the flag. table 20-1 idcdmaen flag 0 0 idcdmaen 0 b 3 b 2 b 1 b 0 0 0 does not use the dma mode (instruction cycle: 2 s) uses the dma mode (instruction cycle: 12 s). (rf 00h) m m
244 m pd17062 sample program remark the set1 or clr1 is not included in the m pd17062 instruction set. they are a built-in macro instruction of the 17k series assembler. they set or reset a one-bit flag. if they are written in a source program as shown at *1, they are expanded during assembly as shown at *2. peek or poke wr, 80h wr, #0010b 80h, wr *1 set1 idcdmaen *2 clr1 idcdmaen peek and poke wr, 80h wr, #1101b 80h, wr instruction cycle: 2 s instruction cycle: 12 s instruction cycle: 2 s m m m
245 m pd17062 b 3 b 2 b 1 b 0 0 0 idcen 0 1 0 turns off the display. turns on the display. (rf 31h) ------ ------ 20.3 idc enable flag the idcen (idc enable) flag is manipulated to start idc operations (turn on the display). the flag is mapped at the lowest bit (#0) of the register file at 31h. table 20-2 idcen flag (1) cautions in turning on the display (a) the idcen flag must be set to 1 (begin displaying), when the vertical sync signal (vsync) is high (vertical flyback time: vsync = low level) after the idcdmaen flag (rf, at 00h, #1) is turned on. (b) do not write data to vram, when the idcen flag is 1 (display turned on). sample program set1 idcdmaen ; sets the dma mode. clr1 idcen ; if the display is on when vram data is to be specified, ; reset the idcen (turn off the display). sets data in vram. ; sets vram data. loop skf1 intvsyn ; makes sure vsync = low level, and sets the idcen. br loop set1 idcen ; turns on the display. --- ---
246 m pd17062 20.4 vram vram is the memory that holds data used to select a picture pattern that the idc displays on a screen such as a tv screen. in the m pd17062, the vram data is allocated at bank1 and bank2 in data memory. one vram data item (8 bits) is held at two adjoining addresses (even and odd address). bank1 and bank2 are each mapped at 112 nibbles of data memory (total of 224 nibbles, or 224 4 bits). that is, up to 112 vram data items can be specified. fig. 20-1 vram configuration vram data consists of 8 bits. of the 8 bits, the upper 2 bits are the id field. the id field indicates the type of vram data. the lower 6 bits are the data field. the data field contains the display data or control data. 01 2345 6789abcdef 0 1 2 3 4 5 6 vram data column address row address even address odd address 4 bits 4 bits (2 data memory locations)
247 m pd17062 fig. 20-2 vram data configuration 20.4.1 id field the id field indicates the type of data in the data field. the data field can hold the following three types of data. (1) character pattern select data (2) carriage return data (3) control data select data table 20-3 id field 20.4.2 character pattern select data the character pattern is the data of an image displayed on a screen such as a tv screen. it is allocated in the crom area (at 0800h to 0f7fh) of program memory. the character pattern select data becomes part (b 9 to b 4 ) of a crom address. in other words, the 6 bits of data in the data field indicate b 9 to b 4 of the crom address. crom consists of bank0 and bank1. note that even if the 6-bit vram data is the same, the crom address varies according to the value of the crombnk (b 0 at 30h). if the data field contains a value of 0 (000000b), the crom address is 080 h (10000000 b) or 0c0 h (11000000 b). specifying the bank of crom selects 080 h or 0c0 h. table 20-4 lists the crom addresses that the vram character pattern select data actually points to. b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 (b 3 )(b 2 )(b 1 )(b 0 )(b 3 )(b 2 )(b 1 )(b 0 ) id field data field even address odd address id field type of data in the data field b 7 b 6 0 0 character pattern select data 0 1 carriage return (return address) to bank1 (from bank1 to bank1, and from bank2 to bank1) 1 0 control data 1 1 carriage return (return address) to bank2 (from bank2 to bank2)
248 m pd17062 table 20-4 vram data (character pattern select data) versus crom addresses vram data crom address vram data crom address (8 bits) bank0 bank1 (8 bits) bank0 bank1 00h 0800h-080eh 0c00h-0c0eh 20h 0a00h-0a0eh 0e00h-0e0eh 01h 0810h-081eh 0c10h-0c1eh 21h 0a10h-0a1eh 0e10h-0e1eh 02h 0820h-082eh 0c20h-0c2eh 22h 0a20h-0a2eh 0e20h-0e2eh 03h 0830h-083eh 0c30h-0c3eh 23h 0a30h-0a3eh 0e30h-0e3eh 04h 0840h-084eh 0c40h-0c4eh 24h 0a40h-0a4eh 0e40h-0e4eh 05h 0850h-085eh 0c50h-0c5eh 25h 0a50h-0a5eh oe50h-0e5eh 06h 0860h-086eh 0c60h-0c6eh 26h 0a60h-0a6eh 0e60h-0e6eh 07h 0870h-087eh 0c70h-0c7eh 27h 0a70h-0a7eh 0e70h-0e7eh 08h 0880h-088eh 0c80h-0c8eh 28h 0a80h-0a8eh 0e80h-0e8eh 09h 0890h-089eh 0c90h-0c9eh 29h 0a90h-0a9eh 0e90h-0e9eh 0ah 08a0h-08aeh 0ca0h-0caeh 2ah 0aa0h-0aaeh 0ea0h-0eaeh 0bh 08b0h-08beh 0cb0h-0cbeh 2bh 0ab0h-0abeh 0eb0h-0ebeh 0ch 08c0h-08ceh 0cc0h-0cceh 2ch 0ac0h-0aceh 0ec0h-0eceh 0dh 08d0h-08deh 0cd0h-0cdeh 2dh 0ad0h-0adeh 0ed0h-0edeh 0eh 08e0h-08eeh 0ce0h-0ceeh 2eh 0ae0h-0aeeh 0ee0h-0eeeh 0fh 08f0h-08feh 0cf0h-0cfeh 2fh 0af0h-0afeh 0ef0h-0efeh 10h 0900h-090eh 0d00h-0d0eh 30h 0b00h-0b0eh 0f00h-0f0eh 11h 0910h-091eh 0d10h-0d1eh 31h 0b10h-0b1eh 0f10h-0f1eh 12h 0920h-092eh 0d20h-0d2eh 32h 0b20h-0b2eh 0f20h-0f2eh 13h 0930h-093eh 0d30h-0d3eh 33h 0b30h-0b3eh 0f30h-0f3eh 14h 0940h-094eh 0d40h-0d4eh 34h 0b40h-0b4eh 0f40h-0f4eh 15h 0950h-095eh 0d50h-0d5eh 35h 0b50h-0b5eh 0f50h-0f5eh 16h 0960h-096eh 0d60h-0d6eh 36h 0b60h-0b6eh 0f60h-0f6eh 17h 0970h-097eh 0d70h-0d7eh 37h 0b70h-0b7eh 0f70h-0f7eh 18h 0980h-098eh 0d80h-0d8eh 38h 0b80h-0b8eh 19h 0990h-099eh 0d90h-0d9eh 39h 0b90h-0b9eh 1ah 09a0h-09aeh 0da0h-0daeh 3ah 0ba0h-0baeh 1bh 09b0h-09beh 0db0h-0dbeh 3bh 0bb0h-0bbeh not to be set 1ch 09c0h-09ceh 0dc0h-0dceh 3ch 0bc0h-0bceh 1dh 09d0h-09deh 0dd0h-0ddeh 3dh 0bd0h-0bdeh 1eh 09e0h-09eeh 0de0h-0deeh 3eh 0be0h-0beeh 1fh 09f0h-09feh 0df0h-0dfeh 3fh 0bf0h-0bfeh
249 m pd17062 sample program if the crom data and vram data are specified as shown above, the display on the screen varies depending on the crom bank. the crom bank is specified by crombnk (b 0 at 30h). the following description applies to the above example. (1) crombnk = 0 display ch appears on the screen. the control data used in this case is control data 1. (2) crombnk = 1 display vo appears on the screen. the control data used in this case is control data 1. 01 234 5 6789a b 800001 40 0 1 crom data vram data 0800h 080fh 0810h 081fh 0c00h 0c0fh 0c10h 0c1fh ? ? ? ? ; control data 1 ; control data 2 ; control data 1 ; control data 2
250 m pd17062 20.4.3 carriage return data the term carriage return data refers to the data pointing to the address of the vram data that specifies the first character in a row on the screen. the carriage return data specifies the end of a display row. when carriage return data appears two times consecutively, it specifies the end of a screen. there are two types of carriage return data; one type is a carriage return to bank1, and the other is a carriage return to bank2. the data in the id field determines whether the data field indicates a carriage return to bank1 or bank2. if the id field contains 01b, it indicates a carriage return to bank1, and if the id field contains 11b, it indicates a carriage return to bank2. the carriage return data consists of 6 bits, the upper 3 bits of which point to the row address of vram and the lower 3 bits of which point to the upper 3 bits of the vram column address. the lowest bit of the vram column address is fixed at 0. if the carriage return data is 010011b, therefore, the vram row address is 010b (2h), and the vram column address is 0110b (6h); namely, they mean the return data to 26h. fig. 20-3 carriage return data configuration b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 id field data field vram row address upper 3 bits of the vram column address
251 m pd17062 fig. 20-4 carriage return data (8 bits including the id field) 01234567 89abcdef 40 41 42 43 44 45 46 47 0 48 49 4a 4b 4c 4d 4e 4f 1 50 51 52 53 54 55 56 57 2 58 59 5a 5b 5c 5d 5e 5f 3 60 61 62 63 64 65 66 67 4 68 69 6a 6b 6c 6d 6e 6f 5 70 71 72 73 74 75 76 77 6 bank1 01234567 89abcdef c0 c1 c2 c3 c4 c5 c6 c7 0 c8 c9 ca cb cc cd ce cf 1 d0 d1 d2 d3 d4 d5 d6 d7 2 d8 d9 da db dc dd de df 3 e0 e1 e2 e3 e4 e5 e6 e7 4 e8 e9 ea eb ec ed ee ef 5 f0 f1 f2 f3 f4 f5 f6 f7 6 bank1
252 m pd17062 20.4.4 control data select data the term control data refers to the data that specifies the character size, display position, and color of a character pattern on the screen. this data is held in crom (at fh). the control data select data is held in vram and selects control data in crom. the 6 bits of the data field correspond to b 9 to b 4 of the crom address. similarly to the pattern select data, the control data select data also requires that a crom bank be specified. a crom bank is specified using crombnk (b 0 at 30h) in the register file. fig. 20-5 relationship between the control data and crom address b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 10 b 11 1 b 0 1111 bank data bank0: 0 bank1: 1 data in vram crom address
253 m pd17062 table 20-5 vram data (control data select data) versus crom addresses vram data crom address vram data crom address (8 bits) bank0 bank1 (8 bits) bank0 bank1 80h 080fh 0c0fh a0h 0a0fh 0e0fh 81h 081fh 0c1fh a1h 0a1fh 0e1fh 82h 082fh 0c2fh a2h 0a2fh 0e2fh 83h 083fh 0c3fh a3h 0a3fh 0e3fh 84h 084fh 0c4fh a4h 0a4fh 0e4fh 85h 085fh 0c5fh a5h 0a5fh 0e5fh 86h 086fh 0c6fh a6h 0a6fh 0e6fh 87h 087fh 0c7fh a7h 0a7fh 0e7fh 88h 088fh 0c8fh a8h 0a8fh 0e8fh 89h 089fh 0c9fh a9h 0a9fh 0e9fh 8ah 08afh 0cafh aah 0aafh 0eafh 8bh 08bfh 0cbfh abh 0abfh 0ebfh 8ch 08cfh 0ccfh ach 0acfh 0ecfh 8dh 08dfh 0cdfh adh 0adfh 0edfh 8eh 08efh 0cefh aeh 0aefh 0eefh 8fh 08ffh 0cffh afh 0affh 0effh 90h 090fh 0d0fh b0h 0b0fh 0f0fh 91h 091fh 0d1fh b1h 0b1fh 0f1fh 92h 092fh 0d2fh b2h 0b2fh 0f2fh 93h 093fh 0d3fh b3h 0b3fh 0f3fh 94h 094fh 0d4fh b4h 0b4fh 0f4fh 95h 095fh 0d5fh b5h 0b5fh 0f5fh 96h 096fh 0d6fh b6h 0b6fh 0f6fh 97h 097fh 0d7fh b7h 0b7fh 0f7fh 98h 098fh 0d8fh b8h 0b8fh 99h 099fh 0d9fh b9h 0b9fh 9ah 09afh 0dafh bah 0bafh 9bh 09bfh 0dbfh bbh 0bbfh not to be set 9ch 09cfh 0dcfh bch 0bcfh 9dh 09dfh 0ddfh bdh 0bdfh 9eh 09efh 0defh beh 0befh 9fh 09ffh 0dffh bfh 0bffh
254 m pd17062 20.4.5 cautions in specifying vram data (1) reset the idcen flag to 0 before specifying vram data. (2) the vram data must begin at 00h in bank1. (3) do not set vram data at 7 h in bank1 or bank2. (4) always set control data at the beginning of a screen. to prevent a program error, control data should be set at the beginning of each row. otherwise, the previous control data remains effective. (5) data setting (a) the character pattern select data should be set at vram addresses sequentially starting at the lowest address so that the corresponding display begins at the upper left corner of the screen. (b) control data can be used up to three times on each row. (c) the character pattern data that is modified by the control data begins after the control data select data. the horizontal start position data and vertical start position data correspond to only a character that follows immediately the control data select data; the other characters are output consecutively. (d) always specify carriage return data at the end of a row. (e) always specify two carriage return data items at the end of a screen.
255 m pd17062 20.5 character rom the crom (character rom) consists of the idc pattern data and control data. the crom data shares the program memory with programs. the crom area has a capacity of 2 ksteps (1920 16 bits). an area not used as crom is used as an ordinary program area. the crom area in rom is at 0800h to 0f7fh. the crom area is divided into bank0 and bank1. a concept of bank applies only to crom. it does not apply to a program area. crom bank0 is 1 kword at from 0800h to 0bffh, and crom bank1 is 896 words at from 0c00h to 0f7fh. the crom bank is switched according to the crombnk flag (b 0 at 30h) in the register file. table 20-6 crom bank remark the crom bank should not be switched when the idcen flag is 1. the register file at 30h can be read- and write-accessed, but the bits other than the crombnk flag (b 0 ) are always 0. because the crom data is mapped in a program memory area, its size is 16 bits. there are two types of crom data. (1) character pattern data (2) control data 20.5.1 character pattern data the character pattern data is a character or graphic pattern. one character consists of 10 horizontal and 15 vertical dots. the corresponding character pattern data consists of 16 bits 15 steps. the data of 10 horizontal dots corresponds to one crom step. 15 steps at addresses 0h to eh in crom form one character pattern data item. the structure of character pattern data varies according to whether the corresponding character has rimming. fig. 20-6 shows the configuration of the character pattern data. the highest bit selects whether there is rimming. set the bit to 0 when the character has no rimming, when the character has rimming, set the bit to 1. for a character with no rimming, the lower 10 bits indicate the dot image of the actually displayed character pattern. b 9 corresponds to the left section of the display, and b 0 to the right section. the bit that corresponds to a bright dot is 1, and the bit that corresponds to a dark dot is 0. for a character with rimming, the character pattern data is 5 bits as shown in fig. 20-6. at this point, two dots of the display pattern correspond to one character pattern data bit. this bit is combined with 10 rim data bits (rim data is specified in one-dot units) to form a character pattern for a character with rimming. with the 17k series assembler, the dcp pseudo instruction can define a character pattern easily. use of this instruction automatically generates the data shown in fig. 20-6, regardless of whether there is rimming. crombnk flag crom bank crom address 0 bank0 0800h-0bffh 1 bank1 0c00h-0f7fh
256 m pd17062 fig. 20-6 character pattern data configuration (a) data for a character with no rimming (b) data for a character with rimming if 2 is to be displayed, the character pattern is set as shown in fig. 20-7. 0 and 1 in the pattern data correspond to n n and n , respectively. in addition, the character size, position, and color are specified by the control data. fig. 20-8 shows an example of the pattern of a character with rimming. fig. 20-7 example of the pattern of a character with no rimming 0 b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 undefined character pattern data 1 b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 character pattern data rim data b 9 b 0 b 15 b 9 b 0 0 h 1 h 2 h 3 h 4 h 5 h 6 h 7 h 8 h 9 h a b c d e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 "0" (no rimming) rom address (in the crom area) undefined h h h h h h h h h pattern data
257 m pd17062 fig. 20-8 example of the pattern of a character with rimming 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 1 1 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 1 0 0 1 1 0 0 0 1 1 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 1 1 0 0 0 1 1 1 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 0 0 0 1 1 0 0 1 0 1 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 b 15 b 9 b 0 b 14 b 9 b 0 b 13 b 12 b 11 b 10 00000000 "1" (rimming) rom address (in the crom area) pattern data rim data pattern data rim data
258 m pd17062 20.5.2 control data the control data specifies the display position, size, and color of a character pattern. it is stored at fh in the crom area. one control data item consists of 16 bits. the highest bit is always 0. fig. 20-9 shows the configuration of the control data. fig. 20-9 control data configuration the control data is provided between two character pattern data items. it has nothing to do with the character pattern data items at addresses before and after the control code. any control data can be specified using data in vram. (1) horizontal size data (b 14 and b 13 of control data) the horizontal size data determines the horizontal size of each image of a character. each character has four image sizes (up to three sizes per row). table 20-7 lists details of the horizontal size data. table 20-7 horizontal size setting 0 b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 (fixed) horizontal size vertical size horizontal position vertical position color horizontal size data size horizontal width maximum number of display b 14 b 13 of a character characters per row 0 0 standard 2.5 m s 16 0 1 double 5.0 m s 8 1 0 triple 7.5 m s 5 1 1 quadruple 10.0 m s4
259 m pd17062 (2) vertical size data (b 12 and b 11 of the control data) the vertical size data determines the vertical size of each image of a character. up to four sizes can be specified on each row. table 20-8 lists details of the vertical size data. the vertical size data specified at the beginning of a row is effective throughout that row. the vertical size data in any other control data for the same row is ignored. table 20-8 vertical size setting (3) horizontal position data (b 10 to b 7 of the control data) the horizontal position data specifies which of the 16 horizontal positions shown in fig. 20-10 the display is to begin at. although each row has 19 horizontal display positions, the display can start only at within 16 character positions from the left side of the screen. the beginning of the row is specified with an absolute column number (column from 0 to 15 in fig. 20-10). the horizontal position data consists of four bits of the control data, with b 10 corresponding to the msb and b 7 corresponding to the lsb, and therefore it takes a value from 0h to fh. value 0h corresponds to column 0, and value fh to column 15. the number of character positions left blank between two characters on the same row is specified by the horizontal position data. in other words, the position of the next character is specified by the number (in hexadecimal) of blank character positions after the current character position. in fig. 20-10, for example, the horizontal position data of a and that of c are 8h and 1h, respectively. if the control data of c is changed to 0, c is displayed in column 9 (at character position 9). if no control data is used after a, c is displayed also in column 9. remark the term number of character positions used in the above description applies when the horizontal size data is 00. if the horizontal size data is changed, the character positions are counted for the new horizontal size data. if the horizontal size data is a double size, for example, one row has only eight character positions. vertical size data size vertical width of a maximum number of display b 12 b 11 character (interlace) characters in the vertical direction 0 0 standard 15h 12 0 1 double 30h 6 1 0 triple 45h 4 1 1 quadruple 60h 3
260 m pd17062 (4) vertical position data (b 6 to b 3 of the control data) the vertical position data specifies which of the 12 rows (vertical positions) shown in fig. 20-10 the display is to begin at. the vertical position data consists of four bits of the control data, with b 6 corresponding to the msb and b 3 corresponding to the lsb, and it takes a value from 0h to dh. value 0h corresponds to row 0, and value dh to column 13. a character position at the beginning of the screen is specified with an absolute row number (row from 0 to 11 in fig. 20-10). the number of rows left blank between two rows is specified by the vertical position data. in other words, the position of the next character is specified by the number (in hexadecimal) of blank rows after the current row. in fig. 20-10, for example, the vertical position data of a and that of b are 6h and 1h, respectively. similarly, the vertical position data of d is 0h. remark the term number of rows used in the above description applies when the vertical size data is 00 (standard size). if the vertical size data is changed, the rows are counted based on the new vertical size data. if the vertical size data is a double size, for example, one screen has only six rows. fig. 20-10 display positions a c b d 0123456789101112131415 row 0 row 1 row 2 row 3 row 4 row 5 row 6 row 7 row 8 row 9 row 10 row 11 row 12 row 13 column column
261 m pd17062 (5) color data (b 2 to b 0 of the control data) the color data specifies the color of a display character. it is output from a specified output pin (r, g, or b pin). table 20-9 lists the correspondence between the color data and the output pins. table 20-10 summarizes the relationships between the color data setting and output colors. table 20-9 color data table 20-10 character color color data character color r g b 0 0 0 black 0 0 1 blue 0 1 0 green 0 1 1 cyan 1 0 0 red 1 0 1 magenta 1 1 0 yellow 1 1 1 white b 2 b 1 b 0 rgb
262 m pd17062 20.5.3 defining display patterns with an assembler with the 17k series assembler, the dcp pseudo instruction can be used to define display patterns easily. how to use the dcp pseudo instruction is described below. (1) instruction format symbol field mnemonic field operand field comment field [label:] dcp expression, display pattern [; comment] (2) explanation (a) the expression takes value 0 or 1. the display pattern written in the second operand specifies whether to use rimming in the display pattern. 0 : no rimming 1 : rimming if the expression does not evaluate to 0 or 1, an error is reported. (b) the display pattern definition consists of 10 characters and can include three different characters, o, #, and (blank). if the display pattern is specified with any other character type or more then 10 characters, an error is reported. each of these three character types corresponds to one dot and has the following meaning: o : bright dot # : rimming : blank when the expression in the first operand evaluates to 0, the display pattern cannot include #.
263 m pd17062 20.6 blank, r, g, and b pins all these pins are cmos push-pull output pins. they output an active-high signal. the blank pin outputs a signal to turn off a broadcasting picture. the r, g, and b pins output character pattern data. if rimming is not specified, the blank signal is the same as the character pattern signal (generated by oring the r, g, and b signals). if rimming is specified, the blank signal output from the blank pin is a waveform enveloping the character pattern signal. fig. 20-11 idc output waveform (a) when rimming is not specified (b) when rimming is specified pattern signal (r, g, and b pins) blank signal (blank pin) pattern signal (r, g, and b pins) blank signal (blank pin)
264 m pd17062 20.7 specifying the display start position idc display start positions (upper left of the screen) can be specified by setting data in the idc start position setting register. up to 16 horizontal and vertical positions can be specified. in other words, the display position of the entire screen can be shifted. the idc start position setting register consists of a 4-bit vertical start position setting register and a 4-bit horizontal start position setting register. the idc start position setting register is mapped at peripheral address 01h. it can be read- and write-accessed using the get and put instructions. note that the idc start position setting register should not be written to when the idcen flag is 1. fig. 20-12 idc start position setting register configuration b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 horizontal start position vertical start position
265 m pd17062 20.7.1 horizontal start position setting register if the horizontal start position setting register contains 0h, the horizontal start position is set 4.25 m s after the trailing edge of the horizontal sync signal. each time the horizontal start position setting register is incremented by one, the horizontal start position shifts to the right by 250 ns; namely the following expression applies. horizontal start position = 4.25 m s + 250 ns (horizontal start position setting data) in fig. 20-13, position a corresponds to the horizontal position setting data 0h. when the horizontal position setting data is changed to 1, the start position shifts to the right by 250 ns (one dot of the minimum-size character), that is position b. (the solid lines indicate the screen when the horizontal position data is 0, and the dotted lines, when the horizontal position data is 1. fig. 20-13 horizontal shifting idc image area 4.25 ab after trailing edge of horizontal synchronizing signal s m
266 m pd17062 20.7.2 vertical start position setting register if the vertical start position setting register contains 0h, the vertical start position is set 17 h (interlace) after the trailing edge of the vertical sync signal. each time the vertical start position setting register is incremented by one, the vertical start position shifts down by 1 h; namely the following expression applies. vertical start position = 17 h + 1 h (vertical start position setting data) in fig. 20-14, position a corresponds to the vertical position setting data 0h. when the vertical position setting data is changed to 1, the start position shifts down by 1 h, that is position b. (the solid lines indicate the screen when the vertical position setting data is 0, and the dotted lines, when the vertical position setting data is 1. fig. 20-14 vertical shifting idc image area 17 h after the trailing edge of the vertical sync signal a b
267 m pd17062 the vertical start position of the display character is determined by the vertical start position register. at this point, the vertical start position (number of horizontal scan lines) depends on the state of the v sync and h sync signals supplied to the m pd17062, as shown in fig. 20-15. in other words, the first h sync signal that comes after the v sync signal rises is counted as 1 h. fig. 20-15 counting the vertical start position v sync h sync h sync # # $ $ % % each circled number corresponds to the number of scan lines.
268 m pd17062 20.8 sample programs the following sample program generates a display shown below. the ram names of vram are defined as follows (tentative): nec ch 02 ....... 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ch 02 display on the tv screen column column row 0 row 5 4 3 2 1 01 23 45 67 0 1 2 vram0 vram1 vram2 vram3 vram4 vram5 vram6 vram7 89abcdef 0 1 2 vram8 vram9 vrama vramb vramc vramd vrame vramf vram map (bank2) vram0 mem 2.00h vram1 mem 2.01h vram2 mem 2.02h vram3 mem 2.03h vram4 mem 2.04h vram5 mem 2.05h vram6 mem 2.06h vram7 mem 2.07h vram8 mem 2.08h vram9 mem 2.09h vrama mem 2.0ah vramb mem 2.0bh vramc mem 2.0ch vramd mem 2.0dh vrame mem 2.0eh vramf mem 2.0fh ; * * ram set * *
269 m pd17062 the sample program follows: program start ; performs initialization such as clearing ram. initialization set1 idcdmaen ; selects the dma mode. clr1 idcen ; turns off the display. ; ; ** channel display routine ** ; clr1 crombnk ; sets the crom bank to 0. ; mov vram0, #1000b ; specifies control code 1. mov vram1, #0000b ; mov vram2, #0 ; specifies display character data c. mov vram3, #0ch ; mov vram4, #0 ; specifies display character data h. mov vram5, #0dh ; mov vram6, #1000b ; specifies control code 2. mov vram7, #0001b ; mov vram8, #0 ; specifies display character data 0. mov vram9, #0 ; mov vrama, #0 ; specifies display character data 2. mov vramb, #2 ; mov vramc, #0100b ; cr (carriage return) mov vramd, #0000b ; mov vrame, #0100b ; cr (carriage return) mov vramf, #0000b ; # loop: skf1 intvsyn ; make sure vsync = low level and turns on the display. br loop set1 idcen ; turns on the display .........
270 m pd17062 at point # , the contents of vram (bank2) are as follows: for this example, the contents of crom are as follows: 0 8 1 0 2 0 3 c 4 0 5 d 6 8 7 1 8 0 9 0 a 0 b 2 c 4 d 0 e 4 f 0 0 1 crom data ; ************************ ; *** ; ************************ image display controller data set *** org 0800h ; ******** ; ******** ; ******** 0 rom address 0800 0800 0000 0801 007c 0802 00fe 0803 01c7 0804 0183 0805 0183 0806 0183 0807 0183 0808 0183 0809 0183 080a 0183 080b 0183 080c 01c7 080d 00fe 080e 007c 080f 058a dcp 0, ' ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dw ooooo ' ooooooo ' ooo ooo ' oo oo ' oo oo ' oo oo ' oo oo ' oo oo ' oo oo ' oo oo ' oo oo ' ooo ooo ' ooooooo ' ooooo ' ; ******* cd1 0000010110001010b ; ** control data 1 ** ; horizontal size = standard, and vertical size = standard ; horizontal position = column 11, and vertical position = row 1 ; color = green (g), and rimming = no ; ?
271 m pd17062 ; ******** ; ******** ; ******** 1 0810 0000 0811 0006 0812 000e 0813 001e 0814 0076 0815 00c6 0816 0186 0817 0006 0818 0006 0819 0006 081a 0006 081b 0006 081c 0006 081d 0006 081e 0006 081f 0082 dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dw oo oo oo oo oo oo oo oo ; ******* cd2 0000000010000010b ; ** control data 2 ** ; horizontal size = standard, and vertical size = standard ; horizontal position = column 1, and vertical position = row 0 ; color = green (g), and rimming = no ; ? oooo oooo oo oo oooooo oooooo ; ******** ; ******** ; ******** 2 0820 0000 0821 007c 0822 00fe 0823 01c7 0824 0183 0825 0003 0826 0007 0827 000e 0828 0038 0829 00e0 082a 01c0 082b 0180 082c 0180 082d 01ff 082e 01ff 082f 0000 dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dw ooo ; ******* cd2 0000000000000000b ; ? ooo ooo ooooooo ooooo ooo oo oo ooo ooo ooo ooo ooo ooo ooooooooo ooooooooo ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ; no use rom address ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
272 m pd17062 ; ******** ; ******** ; ******** 3 0830 0000 0831 007c 0832 00fe 0833 01c7 0834 0183 0835 0003 dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' ; ? ooo ooo ooooooo ooooo ooo oo oo ' ' ' ' ' ' ; ******** ; ******** ; ******** c 08c0 0000 08c1 007f 08c2 00ff 08c3 01c0 08c4 0180 08c5 0180 08c6 0180 08c7 0180 08c8 0180 08c9 0180 08ca 0180 08cb 0180 08cc 01c0 08cd 00ff 08ce 007f 08cf 0000 dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dw oo ; 0000000000000000b ; ? ooo ooo ooooooo ooooo ooo oo oo oo oo oo oo oo ooo ooooooo ooooo ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ; no use oo ooo
273 m pd17062 ; ******** ; ******** ; ******** h 08d0 0000 08d1 0183 08d2 0183 08d3 0183 08d4 0183 08d5 0183 08d6 0183 08d7 01ff 08d8 01ff 08d9 0183 08da 0183 08db 0183 08dc 0183 08dd 0183 08de 0183 08df 0000 dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dcp 0, ' dw oo ; 0000000000000000b ; ? oo oo oo ooooooooo ooooooooo oo oo oo oo oo oo ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ; no use oo oo rom address oo oo oo oo oo oo oo oo oo oo oo oo
274 m pd17062 21. horizontal sync signal counter 21.1 horizontal sync signal counter configuration the horizontal sync signal counter counts the frequency of a horizontal sync signal for tv or similar equipment. when a tv broadcasting signal is received, a prescribed horizontal sync signal is output. using this fact, the horizontal sync signal counter checks whether there is a broadcast station at a particular frequency. the horizontal sync signal counter consists of a 6-bit hsync counter (hsc), gate clock generator, gate control register (hscgt), gate input amplifier, and test gate open register (hscgostt). a signal supplied to the p0b 3 /hscnt pin is amplified by the self-biased input amplifier. the output of the amplifier passes through a gate which opens for a specific time interval specified by the gate control register. after passing through the gate, the amplifier output is counted in the 6-bit hsync counter. when the gate is closed, the hsync counter stops counting and sets 1 in the test gate open register. the hsync counter is a read-only register. reading the hsync counter finds out how many pulses are counted when the gate is open. dividing the number of pulses by the time during which the gate is open (1.69 ms) can obtain the frequency of the horizontal sync signal. the p0b 3 /hscnt pin is also used as an i/o port. it is assigned to the p0b 3 port. when it is used as a horizontal sync signal counter, the p0b 3 must be set as an input port. when it is used as a port, the hscgt must be set with 0000b. when the p0b 3 is used as an input to the horizontal sync signal counter, it is read always as 0. fig. 21-1 horizontal sync signal counter block diagram hscgostt rf92hb 3 (r/w) hscgt rf91hb 1 ,b 0 (r/w) gate clock generator to a port gate input amplifier gate hsync counter selector peripheral address 04h (r)
275 m pd17062 21.2 gate control register (hscgt) the gate control register is a 2-bit register consisting of the hscgt1 and hscgt0 flags used to control the gate. it is mapped in the register file at 11h. the gate control register can be read- and write-accessed through the window register (system register) using the peek and poke instructions, respectively. the following modes can be set up using the gate control register. note the gate clock generator works only when this mode is selected. 21.2.1 gate closed mode in the gate closed mode, the gate is kept closed, disabling the hsc and gate clock generator from operating (the content of the hsync counter does not change). this mode also turns off the bias input to the horizontal sync signal counter, and therefore it should be selected when the port is used. this mode is selected at a power-on reset and a clock stop. 21.2.2 gate open mode when the gate open mode is entered, the gate opens and causes the hsync counter to start counting the input signal after it is reset. when the hsync counter overflows, it goes back to 0. in this mode, the input pin is biased. 21.2.3 1.69 ms gate mode when the 1.69 ms gate mode is entered, the hsync counter is reset and starts counting the input signal after 3.375/2 ms (with an error of 0 to 62.5 m s). the gate is kept open for 1.69 ms. the input pin is biased. if the input signal is high when the gate is opened or closed, it is counted as one. b 3 b 2 b 1 b 0 (rf11h) hscgt0 hscgt1 hscgt2 hscgt3 0 0 1 0 10 1 1 gate closed gate open open-gate time of 1.69 ms note not to be set fixed at 0
276 m pd17062 21.3 hsync counter (hsc) the hsync counter is mapped at peripheral address 04h. it is a 6-bit read-only binary counter. it can be read-accessed through the data buffer using the get instruction. when it overflows, the 6-bit hsync counter goes back to 00h. the hsync counter is reset to 00h at a power-on reset and clock stop. (1) gate open bit (hscgostt) the hscgostt is mapped at the msb (b 3 ) of the register file at 12h. it is always high when the gate with the hsync input is open. note that when the 1.69 ms gate mode is selected, the hscgostt becomes high when the input data is set even if there is no gate clock. 21.4 example of using the horizontal sync signal the following example is a program that uses the horizontal sync signal counter. when the 1.69 ms gate is open clr1 p0bbio3 ; sets p0b3 in input mode. peek wr, 0b6h and wr, #0111b poke 0b6h, wr loop: peek wr, #92h ; makes sure that the gate is closed once. skf wr, #1000b br loop ; mov wr, #0010b ; selects the 1.69 ms gate mode. poke 91h, wr loop2: peek wr, #92h ; makes sure that the gate is closed. skf wr, #1000b br loop2 get dbf, hsc ; reads the content of the hsync counter. ------------------------ ----------- -------- --------
277 m pd17062 22. instruction sets 22.1 outline of instruction sets b 15 b 14 -b 11 0 1 bin hex 0 0 0 0 0 add r, m add m, #n4 0 0 0 1 1 sub r, m sub m, #n4 0 0 1 0 2 addc r, m addc m, #n4 0 0 1 1 3 subc r, m subc m, #n4 0 1 0 0 4 and r, m and m, #n4 0 1 0 1 5 xor r, m xor m, #n4 0 1 1 0 6 or r, m or m, #n4 inc ar inc ix movt dbf, @ar br @ar call @ar ret retsk ei di 0111 7 reti push ar pop ar get dbf, p put p, dbf peek wr, rf poke rf, wr rorc r stop s halt h nop 1 0 0 0 8 ld r, m st m, r 1 0 0 1 9 ske m, #n4 skge m, #n4 1 0 1 0 a mov @r, m mov m, @r 1 0 1 1 b skne m, #n4 sklt m, #n4 1 1 0 0 c br addr (page 0) call addr (page 0) 1 1 0 1 d br addr (page 1) mov m, #n4 1 1 1 0 e skt m, #n 1111 f skf m, #n
278 m pd17062 22.2 instructions legend ar : address register asr : address stack register pointed to by the stack pointer addr : program memory address (11 low-order bits) bank : bank register cmp : compare flag cy : carry flag dbf : data buffer h : halt release condition intef : interrupt enable flag intr : register automatically saved in the stack when an interrupt occurs intsk : interrupt stack register ix : index register mp : data memory row address pointer mpe : memory pointer enable flag m : data memory address specified by m r and m c m r : data memory row address (high-order) m c : data memory column address (low-order) n : bit position (four bits) n4 : immediate data (four bits) page : page (bits 12 and 11 of the program counter) pc : program counter p : peripheral address p h : peripheral address (three high-order bits) p l : peripheral address (four low-order bits) r : general register column address rf : register file address rf r : register file address (three high-order bits) rf c : register file address (four low-order bits) sp : stack pointer s : stop release condition wr : window register ( ) : contents of
279 m pd17062 22.3 list of instruction sets instruction set add subtract logical operation test compare rotation transfer mne- monic add addc inc sub subc or and xor skt skf ske skne skge sklt rorc ld st mov movt operand r, m m, #n4 r, m m, #n4 ar ix r, m m, #n4 r, m m, #n4 r, m m, #n4 r, m m, #n4 r, m m, #n4 m, #n m, #n m, #n4 m, #n4 m, #n4 m, #n4 r r, m m, r @r, m m, @r m, #n4 dbf, @ar instruction code op code 00000 10000 00010 10010 00111 00111 00001 10001 00011 10011 00110 10110 00100 10100 00101 10101 11110 11111 01001 01011 11001 11011 00111 01000 11000 01010 11010 11101 00111 operand m r m r m r m r 000 000 m r m r m r m r m r m r m r m r m r m r m r m r m r m r m r m r 000 m r m r m r m r m r 000 m c m c m c m c 1001 1000 m c m c m c m c m c m c m c m c m c m c m c m c m c m c m c m c 0111 m c m c m c m c m c 0001 r n4 r n4 0000 0000 r n4 r n4 r n4 r n4 r n4 n n n4 n4 n4 n4 r r r r r n4 0000 operation (r) ? (r) + (m) (m) ? (m) + n4 (r) ? (r) + (m) + cy (m) ? (m) + n4 + cy ar ? ar + 1 ix ? ix + 1 (r) ? (r) C (m) (m) ? (m) C n4 (r) ? (r) C (m) C cy (m) ? (m) C n4 C cy (r) ? (r) (m) (m) ? (m) n4 (r) ? (r) (m) (m) ? (m) n4 (r) ? (r) (m) (m) ? (m) n4 cmp ? 0, if (m) n = n, then skip cmp ? 0, if (m) n = 0, then skip (m) C n4, skip if zero (m) C n4, skip if not zero (m) C n4, skip if not borrow (m) C n4, skip if borrow ? cy ? (r) b3 ? (r) b2 ? (r) b1 ? (r) b0 (r) ? (m) (m) ? (r) if mpe = 1: (mp, (r)) ? (m) if mpe = 0: (bank, m r , (r)) ? (m) if mpe = 1: (m) ? (mp, (r)) if mpe = 0: (m) ? (bank, m r , (r)) (m) ? n4 sp ? sp C 1, asr ? pc, pc ? ar, dbf ? (pc), pc ? asr, sp ? sp + 1
280 m pd17062 instruction code mne- monic push pop peek poke get put br call ret retsk reti ei di stop halt nop operand ar ar wr, rf rf, wr dbf, p p, dbf addr @ar addr @ar s h instruction set transfer branch sub- routine op code 00111 00111 00111 00111 00111 00111 01100 01101 00111 11100 00111 00111 00111 00111 00111 00111 00111 00111 00111 000 000 rf r rf r p h p h 000 000 000 001 100 000 001 010 011 100 0000 0000 rf c rf c p l p l 0000 0000 0000 0000 0000 0000 0000 s h 0000 operation operand addr addr 1101 1100 0011 0010 1011 1010 0100 0101 1110 1110 1110 1111 1111 1111 1111 1111 interrupt others sp ? sp C 1, asr ? ar ar ? asr, sp ? sp + 1 wr ? (rf) (rf) ? wr dbf ? (p) (p) ? dbf pc 10-0 ? addr, page ? 0 pc 10-0 ? addr, page ? 1 pc ? ar sp ? sp C 1, asr ? pc, pc 11 ? 0, pc 10-0 ? addr sp ? sp C 1, asr ? pc, pc ? ar pc ? asr, sp ? sp + 1 pc ? asr, sp ? sp + 1 and skip pc ? asr, intr ? intsk, sp ? sp + 1 intef ? 1 intef ? 0 stop halt no operation
281 m pd17062 22.4 built-in macro instructions the following macro instructions are built in the 17k series assembler (as17k). for details, refer to the assembler users guide. legend flag n : flg-type symbol < > : an operand enclosed in < > is optional. mnemonic operand operation n built-in sktn flag 1, flag n if (flag 1) to (flag n) = all 1, then skip 1 n 4 skfn flag 1, flag n if (flag 1) to (flag n) = all 0, then skip 1 n 4 setn flag 1, flag n (flag 1) to (flag n) ? 11 n 4 clrn flag 1, flag n (flag 1) to (flag n) ? 01 n 4 notn flag 1, flag n if (flag n) = 0, then (flag n ) ? 11 n 4 if (flag n) = 1, then (flag n) ? 0 initflg flag 1, if description = not flag n, then (flag n ) ? 01 n 4 <flag n> if description = flag n, then (flag n) ? 1 bankn (bank) ? n0 n 2 macro
282 m pd17062 23. reserved symbols for assembler the reserved m pd17062 symbols for the assembler are listed below. 23.1 system register mem mem mem mem mem mem mem mem flg mem mem mem mem mem mem flg flg flg flg flg 0.74h 0.75h 0.76h 0.77h 0.78h 0.79h 0.7ah 0.7ah 0.7ah.3 0.7bh 0.7bh 0.7ch 0.7dh 0.7eh 0.7fh 0.7eh.0 0.7fh.3 0.7fh.2 0.7fh.1 0.7fh.0 r r r/w r/w r/w r/w r r r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w bits 15 to 12 of the address register bits 11 to 8 of the address register bits 7 to 4 of the address register bits 3 to 0 of the address register window register bank register bits 10 to 8 of the index register high bits 6 to 4 of the memory pointer memory pointer enable flag bits 7 to 4 of the index register bits 3 to 0 of the memory pointer bits 3 to 0 of the index register bits 6 to 3 of the register pointer bits 2 to 0 of the register pointer program status word bcd operation flag compare flag carry flag zero flag index enable flag read/ write description value ar3 ar2 ar1 ar0 wr bank ixh mph mpe ixm mpl ixl rph rpl psw bcd cmp cy z ixe attribute symbol dbf3 dbf2 dbf1 dbf0 mem mem mem mem 0.0ch 0.0dh 0.0eh 0.0fh r/w r/w r/w r/w bits 15 to 12 of the data buffer bits 11 to 8 of the data buffer bits 7 to 4 of the data buffer bits 3 to 0 of the data buffer read/ write description symbol attribute value 23.2 data buffer
283 m pd17062 23.3 port register symbol attribute value read/ description write p0a3 flg 0.70h.3 r/w bit 3 of port 0a p0a2 flg 0.70h.2 r/w bit 2 of port 0a p0a1 flg 0.70h.1 r/w bit 1 of port 0a p0a0 flg 0.70h.0 r/w bit 0 of port 0a p0b3 flg 0.71h.3 r/w bit 3 of port 0b p0b2 flg 0.71h.2 r/w bit 2 of port 0b p0b1 flg 0.71h.1 r/w bit 1 of port 0b p0b0 flg 0.71h.0 r/w bit 0 of port 0b p0c3 flg 0.72h.3 r/w bit 3 of port 0c p0c2 flg 0.72h.2 r/w bit 2 of port 0c p0c1 flg 0.72h.1 r/w bit 1 of port 0c p0c0 flg 0.72h.0 r/w bit 0 of port 0c p0d3 flg 0.73h.3 r note bit 3 of port 0d p0d2 flg 0.73h.2 r note bit 2 of port 0d p0d1 flg 0.73h.1 r note bit 1 of port 0d p0d0 flg 0.73h.0 r note bit 0 of port 0d p1a3 flg 1.70h.3 r/w bit 3 of port 1a p1a2 flg 1.70h.2 r/w bit 2 of port 1a p1a1 flg 1.70h.1 r/w bit 1 of port 1a p1a0 flg 1.70h.0 r/w bit 0 of port 1a p1b3 flg 1.71h.3 r/w bit 3 of port 1b p1b2 flg 1.71h.2 r/w bit 2 of port 1b p1b1 flg 1.71h.1 r/w bit 1 of port 1b p1b0 flg 1.71h.0 r/w bit 0 of port 1b p1c3 flg 1.72h.3 r/w bit 3 of port 1c p1c2 flg 1.72h.2 r/w bit 2 of port 1c p1c1 flg 1.72h.1 r/w bit 1 of port 1c note these are read-only ports. however, even if an output instruction is written, the assembler (ie-17k) does not generate an error message. also, operation is not affected even if it is actually executed on the device.
284 m pd17062 symbol attribute value read/ description write idcdmaen flg 0.80h.1 r/w dma enable flag sp mem 0.81h r/w stack pointer ce flg 0.87h.0 r ce pin status flag sio0ch flg 0.88h.3 r/w sio0 channel selection flag sb flg 0.88h.2 r/w sio0 mode selection flag sio0ms flg 0.88h.1 r/w sio0 clock mode selection flag sio0tx flg 0.88h.0 r/w sio0 tx/rx selection mode btm0zx flg 0.89h.3 r/w timer 0 interrupt mode selection flag btm0ck2 flg 0.89h.2 r/w timer 0 carry ff mode selection flag btm0ck1 flg 0.89h.1 r/w timer 0 carry ff mode selection flag btm0ck0 flg 0.89h.0 r/w timer 0 carry ff mode selection flag intvsyn flg 0.8fh.2 r vsync pin status flag intnc flg 0.8fh.0 r int nc pin status flag hscgt3 flg 0.91h.3 r/w hsync counter mode selection flag (dummy: 0) hscgt2 flg 0.91h.2 r/w hsync counter mode selection flag (dummy: 0) hscgt1 flg 0.91h.1 r/w hsync counter mode selection flag hscgt0 flg 0.91h.0 r/w hsync counter mode selection flag hscgostt flg 0.92h.3 r hsync counter gate open flag pllrfck3 flg 0.93h.3 r/w pll reference clock selection flag pllrfck2 flg 0.93h.2 r/w pll reference clock selection flag pllrfck1 flg 0.93h.1 r/w pll reference clock selection flag pllrfck0 flg 0.93h.0 r/w pll reference clock selection flag intncmd3 flg 0.95h.3 r/w int nc pin status flag (dummy) intncmd2 flg 0.95h.2 r/w int nc pin status flag intncmd1 flg 0.95h.1 r/w int nc pin status flag intncmd0 flg 0.95h.0 r/w int nc pin status flag btm0cy flg 0.97h.0 r timer 0 carry ff status flag sback flg 0.98h.3 r/w serial bus acknowledge flag sio0nwt flg 0.98h.2 r/w sio0 no wait flag sio0wrq1 flg 0.98h.1 r/w sio0 wait request flag sio0wrq0 flg 0.98h.0 r/w sio0 wait request flag iegvsyn flg 0.9fh.2 r/w vsync interrupt edge selection flag iegnc flg 0.9fh.0 r/w intnc interrupt edge selection flag adcch2 flg 0.0a1h.3 r/w a/d converter channel selection flag adcch1 flg 0.0a1h.2 r/w a/d converter channel selection flag adcch0 flg 0.0a1h.1 r/w a/d converter channel selection flag adccmp flg 0.0a1h.0 r/w a/d converter judge flag pllul flg 0.0a2h.0 r pll unlock ff flag p1cgio flg 0.0a7h.0 r/w port 1c i/o selection flag 23.4 register files
285 m pd17062 symbol attribute value read/ description write sio0sf8 flg 0.0a8h.3 r sio0 shift 8 clock flag sio0sf9 flg 0.0a8h.2 r sio0 shift 9 clock flag sbstt flg 0.0a8h.1 r serial bus start test flag sbbsy flg 0.0a8h.0 r serial bus busy flag ipsio0 flg 0.0afh.3 r/w sio0 interrupt permission flag ipvsyn flg 0.0afh.2 r/w vsync interrupt permission flag ipbtm0 flg 0.0afh.1 r/w timer 0 interrupt permission flag ipnc flg 0.0afh.0 r/w intnc interrupt permission flag crombnk flg 0.0b0h.0 r/w crom bank selection flag idcen flg 0.0b1h.0 r/w idc enable flag plulsen3 flg 0.0b2h.3 r/w pll unlock time selection flag (dummy: 0) plulsen2 flg 0.0b2h.2 r/w pll unlock time selection flag (dummy: 0) plulsen1 flg 0.0b2h.1 r/w pll unlock time selection flag plulsen0 flg 0.0b2h.0 r/w pll unlock time selection flag p1bbio3 flg 0.0b5h.3 r/w p1b3 i/o selection flag p1bbio2 flg 0.0b5h.2 r/w p1b2 i/o selection flag p1bbio1 flg 0.0b5h.1 r/w p1b1 i/o selection flag p1bbio0 flg 0.0b5h.0 r/w p1b0 i/o selection flag p0bbio3 flg 0.0b6h.3 r/w p0b3 i/o selection flag p0bbio2 flg 0.0b6h.2 r/w p0b2 i/o selection flag p0bbio1 flg 0.0b6h.1 r/w p0b1 i/o selection flag p0bbio0 flg 0.0b6h.0 r/w p0b0 i/o selection flag p0abio3 flg 0.0b7h.3 r/w p0a3 i/o selection flag p0abio2 flg 0.0b7h.2 r/w p0a2 i/o selection flag p0abio1 flg 0.0b7h.1 r/w p0a1 i/o selection flag p0abio0 flg 0.0b7h.0 r/w p0a0 i/o selection flag sio0imd3 flg 0.0b8h.3 r/w sio0 interrupt mode selection flag (dummy: 0) sio0imd2 flg 0.0b8h.2 r/w sio0 interrupt mode selection flag (dummy: 0) sio0imd1 flg 0.0b8h.1 r/w sio0 interrupt mode selection flag sio0imd0 flg 0.0b8h.0 r/w sio0 interrupt mode selection flag sio0ck3 flg 0.0b9h.3 r/w sio0 shift clock selection flag (dummy: 0) sio0ck2 flg 0.0b9h.2 r/w sio0 shift clock selection flag (dummy: 0) sio0ck1 flg 0.0b9h.1 r/w serial clock selection sio0ck0 flg 0.0b9h.0 r/w serial clock selection irqsio0 flg 0.0bfh.3 r sio0 interrupt request flag irqvsyn flg 0.0bfh.2 r vsync interrupt request flag irqbtm0 flg 0.0bfh.1 r timer 0 interrupt request flag irqnc flg 0.0bfh.0 r int nc interrupt request flag
286 m pd17062 23.5 peripheral hardware register symbol attribute value read/ description write idcorg dat 01h r/w idc start position setting register adcr dat 02h r/w a/d-converter reference-voltage (v ref ) setting register sio0sfr dat 03h r/w sio0 register hsc dat 04h r hsync counter data register pwmr0 dat 05h r/w pwm data register 0 pwmr1 dat 06h r/w pwm data register 1 pwmr2 dat 07h r/w pwm data register 2 pwmr3 dat 08h r/w pwm data register 3 ar dat 40h r/w address register pllr dat 41h r/w pll data register ar_epa1 dat 8040h C call/br/movt instruction operand (epa bit is on) ar_epa0 dat 4040h C call/br/movt instruction operand (epa bit is off) 23.6 others symbol attribute value description dbf dat 0fh fixed operand value for a put/get/movt instruction ix dat 01h fixed operand value for an inc instruction
287 m pd17062 24. electrical characteristics absolute maximum ratings (t a = 25 2 c) parameter symbol rated value unit supply voltage v dd C0.3 to +6.0 v input voltage v i C0.3 to v dd + 0.3 v output voltage v o C0.3 to v dd + 0.3 (excluding p1a 3 to p1a 0 and pwm 3 to pmw 0 ) v output absorption current i o 10 (excluding p1a) ma output withstand voltage v bds 13 (p1a, pwm) v operating temperature t opt1 C20 to +70 c t opt2 C40 to +85 (when idc has stopped) storage temperature v stg C55 to +125 c recommended operation range (t a = C40 to +85 c) parameter symbol conditions min. typ. max. unit supply voltage v dd1 t a = C20 to +70 c (when cpu, pll, and idc are operating) 4.5 5.0 5.5 v v dd2 when cpu and pll are operating (idc is not operating) 4.5 5.0 5.5 v v dd3 when only cpu is operating (pll and idc are not operating) 4.0 5.0 5.5 v data hold voltage v ddr when crystal oscillation has stopped 3.0 5.5 v output withstand voltage v bds p1b 3 -p1b 1 0.0 12.5 v input amplitude v in1 vco 0.7 v dd v p-p supply voltage rise time t rise v dd : 0 ? 4.0 v 500 ms
288 m pd17062 ac characteristics (t a = C40 to +85 c, v dd = 5 v 10 %, rh 70 %) parameter symbol conditions min. typ. max. unit operating frequency f in1 vco sine wave input v in = 0.7 v p-p 0.7 20 mhz f in2 tmin 45 65 hz f in3 hscnt 10 20 khz idc jitter idc g 4.0 8.0 ns idc horizontal start position idc hp from trailing edge of h sync 4.25 m s idc vertical start position idc vp from trailing edge of v sync 17 h a/d converter characteristics (t a = C40 to +85 c, v dd = 5 v 10 %, rh 70 %) parameter symbol conditions min. typ. max. unit a/d conversion 4 bit resolution a/d conversion total t a = C10 to +50 c 0.5 1.0 lsb error tolerance a/d input impedance 1.0 m w dc characteristics (t a = C40 to +85 c, v dd = 5 v 10 %, rh 70 %) parameter symbol conditions min. typ. max. unit supply voltage v dd1 t a = C20 to +85 c (when cpu, pll, and idc are operating) 4.5 5.0 5.5 v v dd2 when cpu and pll are operating (idc is not operating) 4.5 5.0 5.5 v v dd3 when only cpu is operating (pll and idc are not operating) 4.0 5.0 5.5 v supply current i dd4 when only cpu is operating, pll and idc are not 1.0 3.0 ma operating, and halt instruction is being used (20 instructions are executed at 5-ms intervals) data hold voltage v ddr when the timer ff power failure detection method is used 3.0 5.5 v when crystal oscillation has stopped data hold current i ddr when crystal oscillation has stopped t a = 25 c 1.5 10 m a high-level input voltage v ih1 p0a, p0b, p0d, p1b, p1c 0.7v dd v v ih2 ce, int nc , v sync , h sync 0.8v dd ma low-level input voltage v il1 p0a, p0b, p0d, p1b, p1c 0.3v dd v v il2 ce, int nc , v sync , h sync 0.2v dd ma high-level output voltage i oh1 p0a, p0b, p0c, p1b, p1c, C1.0 C2.0 ma red, green, blue, blank v oh = v dd C 1 v low-level output voltage i ol1 p0a, p0b, p0c, p1b, p1c, 1.0 2.0 ma red, green, blue, blank v oh = v dd C 1 v i ol4 p1a v ol = 1 v 15 22 ma high-level input current i ih1 when p0d pull-down resistor is applied v ih = v dd 20 70 150 m a i ih2 vco v ih = v dd 0.1 0.8 1.3 ma output off leakage current i il1 p1a, pwm v oh = 12.5 v 0.5 m a i il2 eo v oh = v dd , v ol = 0 v 1 m a output withstand voltage v bds p1a, pwm 12.5 v
289 m pd17062 25. package drawings 48pin plastic shrink dip (600 mil) item millimeters inches notes 1) each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. n 0.17 0.007 a 44.46 max. 1.751 max. b 1.78 max. 0.070 max. f 0.85 min. 0.033 min. g 3.2?.3 0.126?.012 j 5.72 max. 0.226 max. k 15.24 (t.p.) 0.600 (t.p.) c 1.778 (t.p.) 0.070 (t.p.) d 0.50?.10 0.020 +0.004 ?.005 h 0.51 min. 0.020 min. i 4.31 max. 0.170 max. l 13.2 0.520 m 0.25 0.010 +0.004 ?.003 +0.10 ?.05 m r m i h g f dn c b k p48c-70-600b-1 r 0~15 0~15 2) ltem "k" to center of leads when formed parallel. l a j 124 48 25
290 m pd17062 64 pin plastic qfp ( 14) item millimeters inches f g k n j 1.0 1.6?.2 0.10 0.8 (t.p.) 1.0 q 0.039 0.039 0.063?.008 0.004 0.031 (t.p.) s64gc-80-3be-1 a c note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. d 17.2?.2 0.677?.008 0.125?.075 0.005?.003 a 17.2?.2 0.677?.008 i 0.13 0.005 p 2.7 0.106 s r 3.0 max. 5 ? 0.119 max. 5 ? c 14.0?.2 0.551 +0.009 ?.008 b 14.0?.2 0.551 +0.009 ?.008 h 0.35?.10 0.014 +0.004 ?.005 m 0.15 0.006 +0.004 ?.003 l 0.8?.2 0.031 +0.009 ?.008 +0.10 ?.05 48 49 64 116 32 17 33 m b d f g h j i p n l k m detail of lead end s q r
291 m pd17062 26. recommended soldering conditions the conditions listed below shall be met when soldering the m pd17062. for details of the recommended soldering conditions, refer to our document smd surface mount technology manual (iei-1207) . please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. table 26-1 soldering conditions for surface-mount devices m pd17062gc- -3be: 64-pin plastic qfp (14 14 mm) symbol ir35-207-1 vp15-207-2 C soldering process infrared ray reflow vps partial heating method soldering conditions peak packages surface temperature: 235 ?c reflow time: 30 seconds or less (at 210 ?c or more) maximum allowable number of reflow processes: 1 exposure limit note : 7 days (20 hours of pre-baking is required at 125 ?c afterward.) peak packages surface temperature: 215 ?c reflow time: 40 seconds or less (at 200 ?c or more) maximum allowable number of reflow processes: 2 exposure limit note : 7 days (20 hours of pre-baking is required at 125 ?c afterward.) (1) do not start reflow-soldering the device if its temperature is higher than the room temperature because of a previous reflow soldering. (2) do not use water for flux cleaning before a second reflow soldering. terminal temperature: 300 ?c or less heat time: 3 seconds or less (for each side of device) note exposure limit before soldering after dry-pack package is opened. storage conditions: temperature of 25 ?c and maximum relative humidity at 65% or less caution do not apply more than a single process at once, except for partial heating method. table 26-2 soldering conditions for through hole mount devices m pd17062cu- : 48-pin plastic shrink dip (600 mil) caution in wave soldering, apply solder only to the lead section. care must be taken that jet solder does not come in contact with the main body of the package. wave soldering (only for leads) partial heating method soldering process soldering conditions solder temperature: 260 c or less flow time: 10 seconds or less terminal temperature: 260 c or less heat time: 10 seconds or less
292 m pd17062 name description appendix development tools the following support tools are available for developing programs for the m pd17062. hardware the ie-17k, ie-17k-et, and emu-17k are in-circuit emulators applicable to the 17k series. the ie-17k and ie-17k-et are connected to the pc-9800 series (host machine) or ibm pc/at tm through the rs-232-c interface. the emu-17k is inserted into the extension slot of the pc-9800 series (host machine). use the system evaluation board (se board) corresponding to each product together with one of these in-circuit emulators. simplehost tm , a man machine interface, implements an advanced debug environment. the emu-17k also enables user to check the contents of the data memory in real time. the se-17002 is an se board for the m pd17002 and m pd17062. it is used solely for evaluating the system. it is also used for debugging in combination with the in-circuit emulator. the ep-17002cu is an emulation probe for the 48-pin shrink dip (600 mil). it is used to connect the se board and the target system. the ep-17002gc is an emulation probe for the 64-pin qfp (14 14 mm). it is used with ev-9400gc-64 note 3 to connect the se board to the target system. the ev-9200gc-64 is a conversion socket used to connect the ep-17002gc to the target system. in-circuit emulator ie-17k ie-17k-et note 1 emu-17k note 2 se board (se-17002) emulation probe (ep-17002cu) emulation probe (ep-17002gc) conversion socket (ev-9200gc-64 note 3 ) notes 1. low-end model, operating on an external power supply 2. the emu-17k is a product of ic co., ltd. contact ic co., ltd. (tokyo, 03-3447-3793) for details. 3. the ep-17002gc is supplied together with one ev-9200gc-64. a set of five ev-9200gc-64 is also available.
293 m pd17062 17k series assembler (as17k) device file (as17062) support software (simplehost) m s5a10as17k m s5a13as17k m s7b10as17k m s7b13as17k m s5a10as17062 m s5a13as17062 m s7b10as17062 m s7b13as17062 m s5a10ie17k m s5a13ie17k m s7b10ie17k m s7b13ie17k as17k is an assembler applicable to the 17k series. in developing m pd17062 programs, as17k is used in combination with a device file (as17062). as17062 is a device file for the m pd17062 . it is used together with the assembler (as17k), which is applicable to the 17k series. simplehost, running on the windows tm , provides man- machine-interface in devel- oping programs by using a personal computer and the in-circuit emulator. os part number description distribution media host machine software pc-9800 series ibm pc/at pc-9800 series ibm pc/at pc-9800 series ibm pc/at name ms-dos pc dos windows ms-dos tm pc dos tm ms-dos pc dos remark the following table lists the versions of the operating systems described in the above table. note ms-dos versions 5.00 and 5.00a and pc dos ver. 5.0 are provided with a task swap function. this function, however, cannot be used in these software packages. 5.25-inch, 2hd 3.5-inch, 2hd 5.25-inch, 2hc 3.5-inch, 2hc 5.25-inch, 2hd 3.5-inch, 2hd 5.25-inch, 2hc 3.5-inch, 2hc 5.25-inch, 2hd 3.5-inch, 2hd 5.25-inch, 2hc 3.5-inch, 2hc os versions ms-dos ver. 3.30 to ver. 5.00a note pc dos ver. 3.1 to ver. 5.0 note windows ver. 3.0 to ver. 3.1
294 m pd17062 [memo]
295 m pd17062 cautions on cmos devices # countermeasures against static electricity for all moss caution when handling mos devices, take care so that they are not electrostatically charged. strong static electricity may cause dielectric breakdown in gates. when transporting or storing mos devices, use conductive trays, magazine cases, shock absorbers, or metal cases that nec uses for packaging and shipping. be sure to ground mos devices during assembling. do not allow mos devices to stand on plastic plates or do not touch pins. also handle boards on which mos devices are mounted in the same way. $ cmos-specific handling of unused input pins caution hold cmos devices at a fixed input level. unlike bipolar or nmos devices, if a cmos device is operated with no input, an intermediate-level input may be caused by noise. this allows current to flow in the cmos device, resulting in a malfunction. use a pull-up or pull-down resistor to hold a fixed input level. since unused pins may function as output pins at unexpected times, each unused pin should be separately connected to the v dd or gnd pin through a resistor. if handling of unused pins is documented, follow the instructions in the document. % statuses of all mos devices at initialization caution the initial status of a mos device is unpredictable when power is turned on. since characteristics of a mos device are determined by the amount of ions implanted in molecules, the initial status cannot be determined in the manufacture process. nec has no responsibility for the output statuses of pins, input and output settings, and the contents of registers at power on. however, nec assures operation after reset and items for mode setting if they are defined. when you turn on a device having a reset function, be sure to reset the device first.
296 m pd17062 simplehost is a trademark of nec corporation. ms-dos and windows are trademarks of microsoft corporation. pc/at and pc dos are trademarks of ibm corporation. caution this product contains an i 2 c bus interface circuit. when using the i 2 c bus interface, notify its use to nec when ordering custom code. nec can guarantee the following only when the customer informs nec of the use of the interface: purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: standard, special, and specific. the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices in standard unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 94.11

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